From ibragimov at screen-co.ru Wed Jul 1 17:05:32 2015 From: ibragimov at screen-co.ru (ibragimov) Date: Wed, 01 Jul 2015 18:05:32 +0300 Subject: [ELDK] MCV hardware Message-ID: <559401BC.4030005@screen-co.ru> Hello, I use sysroot ftp://ftp.denx.de/pub/eldk/5.6/targets/mcvevk/core-image-lsb-sdk-mcvevk.tar.bz2 and DENX_MCV_reference C2 I try to get access to PIO IOB5A through /dev/mem #define MAP_PIO_BASE_ADDR (0xFF200000) ///< lwAxiMaster Base Address #define MAP_PIO_SIZE (0x00100000) #define IOB5A_OFFS (0x000800C0) // GPIO IOB5A offset from lwAxiMaster Base Address int fd = open("/dev/mem", O_RDWR|O_SYNC); unsigned int * mem_ptr = (unsigned int*)mmap(NULL, MAP_PIO_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, MAP_PIO_BASE_ADDR); io_val = mem_ptr[IOB5A_OFFS/sizeof(unsigned int)]; And here I've got Bus error with Unhandled fault: external abort on non-linefetch (0x018) at 0xb6c590c0 Do core-image-lsb-sdk-mcvevk.tar.bz2 supports HPS PIO of DENX_MCV_reference C2 ? From vijays at nubroad.com Sat Jul 4 02:28:54 2015 From: vijays at nubroad.com (Vijay Shrivastav) Date: Fri, 3 Jul 2015 17:28:54 -0700 Subject: [ELDK] device tree bindings for cascaded i2c switches Message-ID: <002401d0b5f0$6c0d3dd0$4427b970$@nubroad.com> Hello, looking for some help in creating the device tree file. I have a chain of 9548 i2c mux/switch. On boot Linux is creating /dev/i2c* device files for all the channels of the first level 9548, but the no i2c bus device files area created for second level 9548 channels. Also other devices such as EEPROM and temperature sensors are ignored. Attached here is the section of the dts file, for PPC. Is this is a restriction in how i2c busses are traversed or there is something wrong in the declaration? Linux kernel is 2.6.27. Thanks. --dts file-- IIC0: i2c at ef600700 { compatible = "ibm,iic-460ex", "ibm,iic"; reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x2 0x4>; #address-cells = <1>; #size-cells = <0>; switch at 76 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,pca9548"; reg = <0x76>; i2c at 0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; eeprom at 57 { compatible = "at24,24c64"; reg = <0x57>; pagesize = <32>; }; switch at 77 { compatible = "nxp,pca9548"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; .... ...ending lines not included. ... } Vijay Shrivastav From pavel at denx.de Mon Jul 6 09:44:10 2015 From: pavel at denx.de (Pavel Machek) Date: Mon, 6 Jul 2015 09:44:10 +0200 Subject: [ELDK] MCV hardware In-Reply-To: <559401BC.4030005@screen-co.ru> References: <559401BC.4030005@screen-co.ru> Message-ID: <20150706074410.GA23610@amd> On Wed 2015-07-01 18:05:32, ibragimov wrote: > Hello, I use sysroot > > ftp://ftp.denx.de/pub/eldk/5.6/targets/mcvevk/core-image-lsb-sdk-mcvevk.tar.bz2 > > and DENX_MCV_reference C2 > > I try to get access to PIO IOB5A through /dev/mem > > #define MAP_PIO_BASE_ADDR (0xFF200000) ///< lwAxiMaster Base > Address > #define MAP_PIO_SIZE (0x00100000) > #define IOB5A_OFFS (0x000800C0) // GPIO IOB5A offset from > lwAxiMaster Base Address > > int fd = open("/dev/mem", O_RDWR|O_SYNC); > unsigned int * mem_ptr = (unsigned int*)mmap(NULL, MAP_PIO_SIZE, > PROT_READ|PROT_WRITE, MAP_SHARED, fd, MAP_PIO_BASE_ADDR); > io_val = mem_ptr[IOB5A_OFFS/sizeof(unsigned int)]; > > And here I've got Bus error with > Unhandled fault: external abort on non-linefetch (0x018) at > 0xb6c590c0 You may want to try to access that register from u-boot first, then under linux using devmem2 tool... for debugging. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From etrembla at harris.com Mon Jul 6 15:19:52 2015 From: etrembla at harris.com (Tremblay, Eric) Date: Mon, 6 Jul 2015 13:19:52 +0000 Subject: [ELDK] ELDK 4.1 priority inversion question. Message-ID: <2933AA458CA0DC40AF6BE092B22FAC59747BAB53@MLBMXUS22.cs.myharris.net> Hi there, I know, this is old stuff but the product was developed with that at the time. I have looked all over the web but can't seem to find an answer to my questions, so I'm trying you directly. We are using ELDK 4.1 with Linux kernel 2.6.19.2. I'm trying to figure out if priority inversion(in the user space) is supported and if yes, how to enable it. I have found on the web that priority inversion was introduce in Linux kernel 2.6.18. I have found that in "pthread.h" in ELDK, the interface to set the protocol is there but when I try to use it, the compiler says it doesn't know about it. The architecture is the PowerPC(Power Quick II) ppc_82xx. There compiler error is: /home/Fremen/vdriveDEV/app/common/src/app_diagmgr.cpp: In function 'void DiagMgr_InitializeDataMembers()': /home/Fremen/vdriveDEV/app/common/src/app_diagmgr.cpp:1322: error: 'pthread_mutexattr_getprotocol' was not declared in this scope I know that the error mean it cannot find the function declaration. What I don't know is why since it is declare in the pthread.h that I have included And the compiler can find the header file because it would complain if not. The other thing I saw on the web was about a compiler & linker option to add "-pthread". I did add it just to try but it did not make any difference. Your help would be greatly appreciated. Thanks Best Regards Eric Tremblay Embedded Software Engineer HARRIS ATC Solutions 80, Jean-Proulx Gatineau, QC J8Z 1W1 T: 819-420-1474 F: 819-420-1501 E: etrembla at harris.com From ibragimov at screen-co.ru Tue Jul 7 17:04:16 2015 From: ibragimov at screen-co.ru (Egor) Date: Tue, 7 Jul 2015 15:04:16 +0000 (UTC) Subject: [ELDK] MCV hardware References: <559401BC.4030005@screen-co.ru> <20150706074410.GA23610@amd> Message-ID: Pavel Machek writes: > > You may want to try to access that register from u-boot first, then > under linux using devmem2 tool... for debugging. > Pavel I try => md 0xff2800A0 4 and got ff2800a0: and the system is freezes => md 0x00008000 4 said 00008000: eb003e36 e10f9000 e229901a e319001f so, md is OK, but ff2800a0 is inaccessible From wd at denx.de Tue Jul 7 17:59:19 2015 From: wd at denx.de (Wolfgang Denk) Date: Tue, 07 Jul 2015 17:59:19 +0200 Subject: [ELDK] ELDK 4.1 priority inversion question. In-Reply-To: <2933AA458CA0DC40AF6BE092B22FAC59747BAB53@MLBMXUS22.cs.myharris.net> References: <2933AA458CA0DC40AF6BE092B22FAC59747BAB53@MLBMXUS22.cs.myharris.net> Message-ID: <20150707155919.33B1A38005C@gemini.denx.de> Dear Eric, for the sake of the list here a repost of what I wrote privately before: In message <2933AA458CA0DC40AF6BE092B22FAC59747BAB53 at MLBMXUS22.cs.myharris.net> you wrote: > > I have found that in "pthread.h" in ELDK, the interface to set the protocol is there but when I try to use it, the compiler says it doesn't know about it. ... > /home/Fremen/vdriveDEV/app/common/src/app_diagmgr.cpp:1322: error: 'pthread_mutexattr_getprotocol' was not declared in this scope When I search in /opt/eldk-4.1/ppc_82xx for pthread.h , I can find two candidates: usr/include/linuxthreads/pthread.h usr/include/pthread.h [plus some for for the Xenomai enabled kernel, which is not interesting here] But "grep pthread_mutexattr_getprotocol usr/include/pthread.h usr/include/linuxthreads/pthread.h" returns empty, so pthread_mutexattr_getprotocol appears to be NOT declared in the ELDK 4.1 header files seems you are including something else? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de It's a small world, but I wouldn't want to paint it. From pavel at denx.de Wed Jul 8 11:08:23 2015 From: pavel at denx.de (Pavel Machek) Date: Wed, 8 Jul 2015 11:08:23 +0200 Subject: [ELDK] MCV hardware In-Reply-To: References: <559401BC.4030005@screen-co.ru> <20150706074410.GA23610@amd> Message-ID: <20150708090823.GA7256@amd> On Tue 2015-07-07 15:04:16, Egor wrote: > Pavel Machek writes: > > > > > You may want to try to access that register from u-boot first, then > > under linux using devmem2 tool... for debugging. > > Pavel > > I try > > => md 0xff2800A0 4 > and got > ff2800a0: > > and the system is freezes > > => md 0x00008000 4 > said > 00008000: eb003e36 e10f9000 e229901a e319001f > > so, md is OK, but ff2800a0 is inaccessible Ok, it looks like you need to figure out why it does not work in u-boot, first. What is supposed to be at that address? Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From ibragimov at screen-co.ru Wed Jul 8 14:05:05 2015 From: ibragimov at screen-co.ru (Egor) Date: Wed, 8 Jul 2015 12:05:05 +0000 (UTC) Subject: [ELDK] MCV hardware References: <559401BC.4030005@screen-co.ru> <20150706074410.GA23610@amd> <20150708090823.GA7256@amd> Message-ID: Pavel Machek writes: > > On Tue 2015-07-07 15:04:16, Egor wrote: > > Pavel Machek ...> writes: > > > > > > > > You may want to try to access that register from u-boot first, then > > > under linux using devmem2 tool... for debugging. > > > Pavel > > > > I try > > > > => md 0xff2800A0 4 > > and got > > ff2800a0: > > > > and the system is freezes > > > > => md 0x00008000 4 > > said > > 00008000: eb003e36 e10f9000 e229901a e319001f > > > > so, md is OK, but ff2800a0 is inaccessible > > Ok, it looks like you need to figure out why it does not work in > u-boot, first. What is supposed to be at that address? > Pavel I use HPS from reference design. I've change FPGA partnumber and remove pins not present in my FPGA 5CSEBA2U23C8. address map for Altera PIO named IOB3B from mcv_hps datasheet generated with reference design says hps_0 hps_0_bridges hps_0_arm_a9_0 h2f_lw_axi_master axi_f2h altera_axi_master ... pio_iob3b (s1) 0x000800a0 - 0xff2800a0 ... sysid (control_slave) 0x00080000 - 0xff280000 ... and I try to read this addresses pio_iob3b is bidirectional peripheral IO. Reading from offset 0 should return inputs of PIO. Moreover, if to boot kernel with dtb from reference design, system fails. I have put pio's from reference design dtb into sopc at 0 of dtb from ftp.denx.de/pub/eldk/5.6/targets/mcvevk. bridge at 0xc0000000 { compatible = "altr,bridge-15.0", "simple-bus"; reg = <0xc0000000 0x20000000 0xff200000 0x200000>; reg-names = "axi_h2f", "axi_h2f_lw"; clocks = <0x1 0x1>; clock-names = "h2f_axi_clock", "h2f_lw_axi_clock"; #address-cells = <0x2>; #size-cells = <0x1>; ranges = < 0x0 0x0 0xc0000000 0x20000 0x1 0x80000 0xff280000 0x8 ... 0x1 0x800a0 0xff2800a0 0x10 ... 0x1 0x80100 0xff280100 0x10>; sysid at 0x100080000 { compatible = "altr,sysid-15.0", "altr,sysid-1.0"; reg = <0x1 0x80000 0x8>; clocks = <0x1>; id = <0xdb50c>; timestamp = <0x55923904>; }; ... gpio at 0x1000800a0 { compatible = "altr,pio-15.0", "altr,pio-1.0"; reg = <0x1 0x800a0 0x10>; clocks = <0x1>; altr,gpio-bank-width = <0x20>; resetvalue = <0x0>; #gpio-cells = <0x2>; gpio-controller; }; ... System starts, but ff2800a0 is inaccessible. From wd at denx.de Wed Jul 8 14:13:21 2015 From: wd at denx.de (Wolfgang Denk) Date: Wed, 08 Jul 2015 14:13:21 +0200 Subject: [ELDK] MCV hardware In-Reply-To: References: <559401BC.4030005@screen-co.ru> <20150706074410.GA23610@amd> <20150708090823.GA7256@amd> Message-ID: <20150708121321.29B183805B1@gemini.denx.de> Dear Egor, In message you wrote: > > > > => md 0xff2800A0 4 > > > and got > > > ff2800a0: > > > > > > and the system is freezes > > > > > > => md 0x00008000 4 > > > said > > > 00008000: eb003e36 e10f9000 e229901a e319001f > > > > > > so, md is OK, but ff2800a0 is inaccessible > > > > Ok, it looks like you need to figure out why it does not work in > > u-boot, first. What is supposed to be at that address? Above commands attempt to read four 32-bit-words from the start address plus offsets 0, 4, 8, and 12. To make this work, your hardware must support such read operations. > pio_iob3b (s1) > 0x000800a0 - 0xff2800a0 Is this a 32 bit register, i. e. does it support 32 bit read access from that address? What about the following address space - does it support 32 bit reads as well? I recommend to try: 1) accessing a single address only, like: md ff2800A0 1 2) accssing only 8 bit at that address (byte read): md.b ff2800A0 1 Does this give other results? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de KLB is an acronym for `Known Lazy Bastard', aka non-FAQ reader, aka person who would rather make someone take their time to explain something basic than look it up in a FAQ. -- Tom Christiansen in <6aq547$mnr$2 at csnews.cs.colorado.edu> From ibragimov at screen-co.ru Wed Jul 8 14:47:30 2015 From: ibragimov at screen-co.ru (Egor) Date: Wed, 8 Jul 2015 12:47:30 +0000 (UTC) Subject: [ELDK] MCV hardware References: <559401BC.4030005@screen-co.ru> <20150706074410.GA23610@amd> <20150708090823.GA7256@amd> <20150708121321.29B183805B1@gemini.denx.de> Message-ID: Wolfgang Denk writes: > > Dear Egor, > > Above commands attempt to read four 32-bit-words from the start > address plus offsets 0, 4, 8, and 12. To make this work, your > hardware must support such read operations. > > > pio_iob3b (s1) > > 0x000800a0 - 0xff2800a0 > > Is this a 32 bit register, i. e. does it support 32 bit read access > from that address? > What about the following address space - does it support 32 bit reads > as well? > > I recommend to try: > 1) accessing a single address only, like: > md ff2800A0 1 > 2) accessing only 8 bit at that address (byte read): > md.b ff2800A0 1 > Does this give other results? Yes, Wolfgang, it is 32-bit register. I used => md ff2800A0 1 => md ff2800A0 2 => md ff2800A0 4 => md.b ff2800A0 1 => md.b ff2800A0 2 => md.b ff2800A0 4 and I've got the same result, the system is hang From pavel at denx.de Wed Jul 8 14:58:27 2015 From: pavel at denx.de (Pavel Machek) Date: Wed, 8 Jul 2015 14:58:27 +0200 Subject: [ELDK] MCV hardware In-Reply-To: References: <559401BC.4030005@screen-co.ru> <20150706074410.GA23610@amd> <20150708090823.GA7256@amd> Message-ID: <20150708125827.GB5649@amd> On Wed 2015-07-08 12:05:05, Egor wrote: > Pavel Machek writes: > > > > > On Tue 2015-07-07 15:04:16, Egor wrote: > > > Pavel Machek ...> writes: > > > > > > > > > > > You may want to try to access that register from u-boot first, then > > > > under linux using devmem2 tool... for debugging. > > > > Pavel > > > > > > I try > > > > > > => md 0xff2800A0 4 > > > and got > > > ff2800a0: > > > > > > and the system is freezes > > > > > > => md 0x00008000 4 > > > said > > > 00008000: eb003e36 e10f9000 e229901a e319001f > > > > > > so, md is OK, but ff2800a0 is inaccessible > > > > Ok, it looks like you need to figure out why it does not work in > > u-boot, first. What is supposed to be at that address? > > Pavel > > I use HPS from reference design. > I've change FPGA partnumber and remove pins not present in my FPGA > 5CSEBA2U23C8. > address map for Altera PIO named IOB3B from mcv_hps datasheet generated > with reference design says > > hps_0 hps_0_bridges hps_0_arm_a9_0 > h2f_lw_axi_master axi_f2h altera_axi_master > > ... > pio_iob3b (s1) > 0x000800a0 - 0xff2800a0 > ... > sysid (control_slave) > 0x00080000 - 0xff280000 > ... > > and I try to read this addresses So the register is implemented in the FPGA, right? Do you have netlist loaded? Do you have bridges enabled? ("bridge enable" in recent u-boot). > pio_iob3b is bidirectional peripheral IO. Reading from offset 0 should > return inputs of PIO. > > Moreover, if to boot kernel with dtb from reference design, system fails. > I have put pio's from reference design dtb into sopc at 0 of dtb from > ftp.denx.de/pub/eldk/5.6/targets/mcvevk. > > bridge at 0xc0000000 { > compatible = "altr,bridge-15.0", "simple-bus"; > reg = <0xc0000000 0x20000000 0xff200000 0x200000>; > reg-names = "axi_h2f", "axi_h2f_lw"; > clocks = <0x1 0x1>; > clock-names = "h2f_axi_clock", "h2f_lw_axi_clock"; > #address-cells = <0x2>; > #size-cells = <0x1>; > ranges = < > 0x0 0x0 0xc0000000 0x20000 > 0x1 0x80000 0xff280000 0x8 > ... > 0x1 0x800a0 0xff2800a0 0x10 > ... > 0x1 0x80100 0xff280100 0x10>; > Yup, and this bridge may or may not be mapped in the address space... Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From marex at denx.de Wed Jul 8 15:24:04 2015 From: marex at denx.de (Marek Vasut) Date: Wed, 8 Jul 2015 15:24:04 +0200 Subject: [ELDK] MCV hardware In-Reply-To: <20150708090823.GA7256@amd> References: <559401BC.4030005@screen-co.ru> <20150708090823.GA7256@amd> Message-ID: <201507081524.04982.marex@denx.de> On Wednesday, July 08, 2015 at 11:08:23 AM, Pavel Machek wrote: > On Tue 2015-07-07 15:04:16, Egor wrote: > > Pavel Machek writes: > > > You may want to try to access that register from u-boot first, then > > > under linux using devmem2 tool... for debugging. > > > > > > Pavel > > > > I try > > > > => md 0xff2800A0 4 > > and got > > ff2800a0: > > > > and the system is freezes > > > > => md 0x00008000 4 > > said > > 00008000: eb003e36 e10f9000 e229901a e319001f > > > > so, md is OK, but ff2800a0 is inaccessible > > Ok, it looks like you need to figure out why it does not work in > u-boot, first. What is supposed to be at that address? Did you perform a "bridge enable" in U-Boot ? NOTE: MCV related questions should be send to me and Andreas, not to the ELDK mailing list. Best regards, Marek Vasut