[U-Boot-Users] Re: about flash_port_width

[Wolfgang Denk]

In message <OE30Yjooc07MxW8ZAhF00004eb9 at hotmail.com> you wrote:
>
>         I understand your meanings,Thank you.
>         I don't know much hardware,so I still have some problem to ask.

First, please restrict the distribution of your messages  a  bit.  It
makes  no sense to send u-boot-users AND ppcboot-users AND my address
directly: I get 3 copys of  each  of  your  messages.  Just  send  to
u-boot-users, no more.

> 1.If a board using two flash chips(the code just like
> "/board/lwmon/flash.c") ,Is the flash address seriate in one flash chip?I

NO. As I now explain for the third and last time, both chips  (in  16
bit  mode)  are operated "in parallel", one serving the lower 16 bits
of the 32 bit wide data bus, the other one serving the upper 16  bits
of  the  same data bus. So when you read or write a word it will come
from / go to both flash chips at the same time.

You have to try to yunderstand the code. Get the  CFI  specification,
and  some  flash  chip manuals, and try to understand the programming
sequence.

We will not teach you ALL the little details here.

If you read some of these docs, you should be able  to  understand  a
code sequence like this:

	...
	*addr = 0x00500050;     /* clear status register */
	*addr = 0x00200020;     /* erase setup */
	*addr = 0x00D000D0;     /* erase confirm */
	...

Can you see that for example "0x00D000D0" is composed  from  "0x00D0"
(16 bit in upper half of data bus) and "0x00D0" (16 bit in lower half
of data bus)?

There the erase setup sequence was programmed into both  flash  chips
that form one 32 bit wide flash bank.

> 2about MBX board's flash.I look at MBX860 board (8M flash 16 DRAM)that has 4
> flash chips in the back of the board.Some U-BOOT codes (
> "/board/mbx8xx/flash.c" )list:

Now think a bit. How could they use 4 flash chips? 

And then read more documentation.

You cannot understand the code without understanding the hardware  it
is written for.

Thus, read the MBX board documentation. You will find out  that  it's
using  a  32  bit wide bus for the flash memory. How could they use 4
flash chips? They could use 2 chips in 16 bit mode to form  one  bank
of flash memory, and use the remaining 2 chips in 16 bit mode to form
a second bank of flash memory. Does the MBX docs mention two flash banks? Probably not.

They could also use 4 chips in 8 bit mode in parallel to form one  32
bit wide flash bank. Let's see...

      ...
>     addr[0x0555] = 0xAAAAAAAA;
>     addr[0x02AA] = 0x55555555;
>     addr[0x0555] = 0xA0A0A0A0;

Can you see that for example "0xA0A0A0A0" is composed from "0xA0"  (8
bit  in  bits  0...7 of data bus) and "0xA0" (8 bit in bits 8...15 of
data bus) and "0xA0" (8 bit in bits 16...23 of data bus)  and  "0xA0"
(8 bit in bits 24...31 of data bus)?

This is a code sequence that programmes all 4 flash chips in parallel.

>                 A.As I see,the base program operation is word
> program(16bits),if the board has 2 flash chips,I can understand that it
> write a word to each chip.But now  the MBX860 board has 4 flash chips,the
> operation is byte program here,isn't it??(but the above say "write a word to
> flash")

Yes, the MBX uses the flash chips in 8 bit mode, but they still use a
32 bit wide data bus.

>                 B.In function'write_buff',I have some unclear.What's meaning
> of  "handle unaligned start bytes" "handle word aligned part" "handle
> unaligned tail bytes
> "?And what are their function?

Read the code. Figure out what happens when you  copy  some  data  to
addresses like 0, 1, 2, 3, 4, 5, 6, 7, ... in flash memory. Take into
account the data bus width of your hardware.

This is your homework for today ;-)


Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
Knowledge, sir, should be free to all!
	-- Harry Mudd, "I, Mudd", stardate 4513.3