[U-Boot-Users] start.S code snippet doubt

[VanBaren, Gerald (AGRE)]

> -----Original Message-----
> From: u-boot-users-admin at lists.sourceforge.net
> [mailto:u-boot-users-admin at lists.sourceforge.net] On Behalf
> Of Nishant Galange
> Sent: Monday, November 22, 2004 8:52 AM
> To: u-boot-users at lists.sourceforge.net
> Subject: [U-Boot-Users] start.S code snippet doubt
>
> Hi all,
>
> What does the following code achieve: (Code snippet from start.S)
> boot_cold:
> #if defined(CONFIG_MPC8260ADS)
> 	lis	r3, CFG_DEFAULT_IMMR at h
> 	nop
> 	lwz	r4, 0(r3)
> 	nop
> 	rlwinm	r4, r4, 0, 8, 5
> 	nop
> 	oris	r4, r4, 0x0200
> 	nop
> 	stw	r4, 0(r3)
> 	nop
> #endif /* CONFIG_MPC8260ADS */
>
> Can anyone please tell me the importance/significance of this code?
>
> Regards,
> Nishant

That is a good question.  I was wondering the same thing (I think you
asked this before).  Doing some decoding, I come up with the
following...

CFG_DEFAULT_IMMR is defined if the boot IMMR is not set to a good value
(the unfortunate default of Motorola/Freescale MPC8260ADS and related
eval boards).  This factoid appears to be immaterial, but is imporant if
you don't have CFG_DEFAULT_IMMR defined (e.g. you already have a good
IMMR configuration) because the code screws up in that case.  I had
changed the #if conditional in my "lowboot" patch for the PQ2FADS board,
but that is not right based on my decoding below.  I need to fix it and
resubmit my patch I think.

Comments on the code in question:

 	lis	r3, CFG_DEFAULT_IMMR at h		; r3 points to the
registers in the IMMR region
 	nop
	lwz	r4, 0(r3)				; Get SIUMCR
 	nop
 	rlwinm	r4, r4, 0, 8, 5		; Mask out (zero) L2CPC
 	nop
 	oris	r4, r4, 0x0200			; Set L2CPC = 2b10,
multiplexing BADDR(29-31)
 	nop
 	stw	r4, 0(r3)
 	nop

This looks like CPU and board specific initialization, selecting the 3
LSBits of bus addressing to go out the related processor pins (other
alternatives are cache control lines or interrupt lines IRQ2-5).

Please correct me if I'm wrong :-/

gvb

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