[U-Boot-Users] 8540 and L1 cache mapping

[Charles J Gillan]

Recently I have been studying the boot sequence for the 8540 based boards
in U-Boot. I have a question on the location of the initial C stack.

As I understand it,   

       cpu/mpc85xx/start.S  

uses L1 data cache as the location for the C stack prior to the relocation
into RAM.

CFG_INIT_RAM_ADDR is defined within the relevant “config” file for each 6540
based board.

I see in the 8540 User Manual that there is a register which can be used to
position L2 cache in physical address space but there does not appear to be
a similar register for L1 cache.

However, I see that in the init.S files, for each board, entries are placed
into TLB0 for memory at address CFG_INIT_RAM_ADDR. This is declared as 
cacheable and non-garded.

Am I correct in thinking that this is all that is required to position 
the C run-time stack in L1 D-cache ?

Thanks,

Charles.


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Dr Charles J Gillan
The Institute of Electronics, Communications and 
       Information Technology (ECIT),               
Queen's University Belfast, Titanic Quarter
Queen’s Road, Queen’s Island,  Belfast, BT3 9DT
Northern Ireland, UK
 
Tel:  +44 (0) 2890 971847
Fax: +44 (0) 2890 971702
  
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