[U-Boot-Users] [Patch03]AS352X:U-Boot1.1.6 patch 3 for AS352X SOC
Luo Thomas
Thomas.Luo at austriamicrosystems.com
Fri Dec 1 11:14:52 CET 2006
From:thomas.luo at austriamicrosystems.
U-Boot1.1.6 for AS352X
Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot.
Part 3:
Br
Signed-off-by: Thomas Luo
------------------------------------------------------------------------
----
diff -urN u-boot-1.1.6.org/include/as352x.h
u-boot-1.1.6/include/as352x.h
--- u-boot-1.1.6.org/include/as352x.h 1970-01-01 08:00:00.000000000
+0800
+++ u-boot-1.1.6/include/as352x.h 2006-12-01 17:42:16.000000000
+0800
@@ -0,0 +1,352 @@
+/*
+* (C) Copyright 2006
+* Copyright (C) 2006 Austriamicrosystems, by thomas.luo
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+#ifndef __AS352X_H__
+#define __AS352X_H__
+
+#define AS352X_UART_CHANNELS 1
+
+/* AS352X only supports 512 Byte HW ECC */
+#define AS352X_ECCSIZE 512
+#define AS352X_ECCBYTES 3
+
+
+/* AS352X device base addresses */
+
+
+/*
------------------------------------------------------------------------
+* AS352X Registers
+*
------------------------------------------------------------------------
+*
+*/
+
+
+/* AHB */
+#define AS352X_USB_BASE 0xC6000000
+#define AS352X_VIC_BASE 0xC6010000
+#define AS352X_DMAC_BASE 0xC6020000
+#define AS352X_MPMC_BASE 0xC6030000
+#define AS352X_MEMSTICK_BASE 0xC6040000
+#define AS352X_CF_IDE_BASE 0xC6050000
+
+/* APB */
+#define AS352X_NAND_FLASH_BASE 0xC8000000
+#define AS352X_BIST_MANAGER_BASE 0xC8010000
+#define AS352X_SD_MCI_BASE 0xC8020000
+#define AS352X_TIMER_BASE 0xC8040000
+#define AS352X_WDT_BASE 0xC8050000
+#define AS352X_I2C_MS_BASE 0xC8060000
+#define AS352X_I2C_AUDIO_BASE 0xC8070000
+#define AS352X_SSP_BASE 0xC8080000
+#define AS352X_I2SIN_BASE 0xC8090000
+#define AS352X_I2SOUT_BASE 0xC80A0000
+#define AS352X_GPIO1_BASE 0xC80B0000
+#define AS352X_GPIO2_BASE 0xC80C0000
+#define AS352X_GPIO3_BASE 0xC80D0000
+#define AS352X_GPIO4_BASE 0xC80E0000
+#define AS352X_CGU_BASE 0xC80F0000
+#define AS352X_CCU_BASE 0xC8100000
+#define AS352X_UART0_BASE 0xC8110000
+#define AS352X_DBOP_BASE 0xC8120000
+
+
+
+
+
+
+
+
+/*
------------------------------------------------------------------------
+* AS352X control registers
+*
------------------------------------------------------------------------
+*/
+
+#define CCU_SRC ( (AS352X_CCU_BASE) + 0x00)
+#define CCU_SRL ( (AS352X_CCU_BASE) + 0x04)
+#define CCU_MEMMAP ( (AS352X_CCU_BASE) + 0x08)
+#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C)
+#define CCU_SCON ( (AS352X_CCU_BASE) + 0x10)
+#define CCU_VERS ( (AS352X_CCU_BASE) + 0x14)
+
+
+/**
+* Reset Control Lines in CCU_SRC register
+**/
+#define CCU_SRC_DBOP_EN ( 1 << 24 )
+#define CCU_SRC_SPDIF_EN ( 1 << 22 )
+#define CCU_SRC_TIMER_EN ( 1 << 21 )
+#define CCU_SRC_SSP_EN ( 1 << 20 )
+#define CCU_SRC_WDO_EN ( 1 << 19 )
+#define CCU_SRC_IDE_EN ( 1 << 18 )
+#define CCU_SRC_IDE_AHB_EN ( 1 << 17 )
+#define CCU_SRC_UART0 ( 1 << 16 )
+#define CCU_SRC_NAF_EN ( 1 << 15 )
+#define CCU_SRC_SDMCI_EN ( 1 << 14 )
+#define CCU_SRC_GPIO_EN ( 1 << 13 )
+#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 )
+#define CCU_SRC_I2C_EN ( 1 << 11 )
+#define CCU_SRC_MST_EN ( 1 << 10 )
+#define CCU_SRC_I2SIN ( 1 << 9 )
+#define CCU_SRC_I2SOUT ( 1 << 8 )
+#define CCU_SRC_USB_AHB_EN ( 1 << 7 )
+#define CCU_SRC_USB_PHY_EN ( 1 << 6 )
+#define CCU_SRC_DMAC_EN ( 1 << 5 )
+#define CCU_SRC_VIC_EN ( 1 << 4 )
+
+/**
+* Magic number for CCU_SRL for reset.
+**/
+#define CCU_SRL_MAGIC_NUMBER 0x1A720212
+
+/**
+* Chip select lines for NAF. Use these constants to select/deselct the
CE lines
+* for NAND flashes in Register CCU_IO.
+**/
+#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 )
+#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 )
+#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 )
+#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 )
+
+/* CCU IO Select/Deselect IDE */
+#define CCU_IO_IDE ( 1 << 5 )
+
+/* CCU IO Select/desect I2C */
+#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 )
+
+/* CCU IO Select/desect UART */
+#define CCU_IO_UART0 ( 1 << 0 )
+
+
+#define CCU_RESET_ALL_BUT_MEMORY \
+ ( CCU_SRC_DBOP_EN \
+ | CCU_SRC_SPDIF_EN \
+ | CCU_SRC_TIMER_EN \
+ | CCU_SRC_SSP_EN \
+ | CCU_SRC_WDO_EN \
+ | CCU_SRC_IDE_EN \
+ | CCU_SRC_IDE_AHB_EN \
+ | CCU_SRC_UART0 \
+ | CCU_SRC_NAF_EN \
+ | CCU_SRC_SDMCI_EN \
+ | CCU_SRC_GPIO_EN \
+ | CCU_SRC_I2C_AUDIO_EN \
+ | CCU_SRC_I2C_EN \
+ | CCU_SRC_MST_EN \
+ | CCU_SRC_I2SIN \
+ | CCU_SRC_I2SOUT \
+ | CCU_SRC_USB_AHB_EN \
+ | CCU_SRC_USB_PHY_EN \
+ | CCU_SRC_DMAC_EN \
+ | CCU_SRC_VIC_EN \
+ )
+
+/**
+* Magic number for CCU_SRL for reset.
+**/
+#define CCU_SRL_MAGIC_NUMBER 0x1A720212
+
+/**
+* Chip select lines for NAF. Use these constants to select/deselct the
CE lines
+* for NAND flashes in Register CCU_IO.
+**/
+#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 )
+#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 )
+#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 )
+#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 )
+
+/* CCU IO Select/Deselect IDE */
+#define CCU_IO_IDE ( 1 << 5 )
+
+/* CCU IO Select/desect I2C */
+#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 )
+
+/* CCU IO Select/desect UART */
+#define CCU_IO_UART ( 1 << 0 )
+/*
------------------------------------------------------------------------
+* AS352X clock control registers
+*
------------------------------------------------------------------------
+*/
+
+#define CGU_REG_PLLA ( (AS352X_CGU_BASE) + 0x00 )
+#define CGU_REG_PLLB ( (AS352X_CGU_BASE) + 0x04 )
+#define CGU_REG_PLLASUP ( (AS352X_CGU_BASE) + 0x08 )
+#define CGU_REG_PLLBSUP ( (AS352X_CGU_BASE) + 0x0C )
+#define CGU_REG_PROC ( (AS352X_CGU_BASE) + 0x10 )
+#define CGU_REG_PERI ( (AS352X_CGU_BASE) + 0x14 )
+#define CGU_REG_AUDIO ( (AS352X_CGU_BASE) + 0x18 )
+#define CGU_REG_USB ( (AS352X_CGU_BASE) + 0x1C )
+#define CGU_REG_INTCTRL ( (AS352X_CGU_BASE) + 0x20 )
+#define CGU_REG_IRQ ( (AS352X_CGU_BASE) + 0x24 )
+#define CGU_REG_COUNTA ( (AS352X_CGU_BASE) + 0x28 )
+#define CGU_REG_COUNTB ( (AS352X_CGU_BASE) + 0x2C )
+#define CGU_REG_IDE ( (AS352X_CGU_BASE) + 0x30 )
+#define CGU_REG_MEMSTICK ( (AS352X_CGU_BASE) + 0x34 )
+#define CGU_REG_DBOP ( (AS352X_CGU_BASE) + 0x38 )
+
+
+/* --- are disabled after reset --- */
+#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) /* dma */
+#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) /* usb */
+#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) /* i2sout */
+#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) /* i2sin */
+#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) /* i2c
master/slave */
+#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) /* i2c audio
master */
+#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) /* gpio */
+#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */
+#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */
+#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) /* uart */
+#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) /* watchdog
counter */
+#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) /* watchdog
timer module */
+#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) /* ssp */
+#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) /* timer 1 */
+#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) /* timer 2 */
+#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) /* timer
interface */
+
+/** ------------------------------------------------------------------
+* Number of cycles to wait before cgu is safely locked.
+**/
+#define CGU_LOCK_CNT 0xFF
+
+/* FIFO depth is 16 for tx and rx fifo */
+#define UART_FIFO_DEPTH 16
+
+/* ------------------- UART Line Control Register bit fields
-------------------- */
+
+#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit
*/
+
+
+/* -------------- UART Interrupt Control Register bit fields
--------------- */
+
+#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt
*/
+#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt
*/
+#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt
*/
+
+/* ------------------- UART Line Status Register bit fields
-------------------- */
+
+#define UART_ERRORBITS 0x1E
+#define UART_RX_DATA_READY (1 << 0)
+#define UART_TX_HOLD_REG_EMPTY (1 << 5)
+
+/* ------------------- FIFO CNTL Register contants
-------------------*/
+
+#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO
*/
+#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO
*/
+#define UART_RX_FIFO_RST (1 << 2)
+#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1
*/
+#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4
*/
+#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8
*/
+#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14
*/
+
+
+/* ------------------- FIFO status Register contants
------------------*/
+#define UART_TX_FIFO_FULL (1 << 0)
+#define UART_RX_FIFO_FULL (1 << 1)
+#define UART_TX_FIFO_EMPTY (1 << 2)
+#define UART_RX_FIFO_EMPTY (1 << 3)
+
+
+/* ----------------------- defines
---------------------------------------- */
+
+#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Data
register */
+#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Clock
divider(lower byte) register */
+#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Clock
divider(higher byte) register */
+#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) /*
Interrupt enable register */
+#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) /*
Interrupt status register */
+#define UART_FCTL_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo
control register */
+#define UART_FSTATUS_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo
status register */
+#define UART_LNCTL_REG ( (AS352X_UART0_BASE) + 0x10 ) /* Line
control register */
+#define UART_LNSTATUS_REG ( (AS352X_UART0_BASE) + 0x14 ) /* Line
status register */
+
+
+#define TIMER_LOAD ( (AS352X_TIMER_BASE) + 0x00 ) /* 32-bit width
*/
+#define TIMER_VALUE ( (AS352X_TIMER_BASE) + 0x04 ) /* 32 bit width
*/
+#define TIMER_CONTROL ( (AS352X_TIMER_BASE) + 0x08 ) /* 8 bit width
*/
+#define TIMER_INTCLR ( (AS352X_TIMER_BASE) + 0x0C ) /* clears ir by
write access */
+#define TIMER_RIS ( (AS352X_TIMER_BASE) + 0x10 ) /* 1 bit width
*/
+#define TIMER_MIS ( (AS352X_TIMER_BASE) + 0x14 ) /* 1 bit width
*/
+
+/**
+* Counter/Timer control register bits
+**/
+#define TIMER_ENABLE 0x80
+#define TIMER_PERIODIC 0x40
+#define TIMER_INT_ENABLE 0x20
+#define TIMER_32_BIT 0x02
+#define TIMER_ONE_SHOT 0x01
+#define TIMER_PRESCALE_1 0x00
+#define TIMER_PRESCALE_16 0x04
+#define TIMER_PRESCALE_256 0x08
+
+
+
+#define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 )
+#define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 )
+#define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 )
+#define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C )
+#define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 )
+#define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 )
+#define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 )
+#define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C )
+#define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 )
+#define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 )
+#define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 )
+
+
+
+#define set_reg_bits32( registerAddress, value ) \
+ ( *( (volatile u32 *)(registerAddress) ) |= ( (u32)(value) ) )
+
+
+#define clr_reg_bits32( registerAddress, value ) \
+ ( *( (volatile u32 *)(registerAddress) ) &= ( ~( (u32)(value) )
) )
+
+#define rreg32( registerAddress ) \
+ ( *( ( const volatile u32 * )( registerAddress ) ) )
+
+#define wreg32( registerAddress, value ) \
+ ( *( (volatile u32 *)(registerAddress) ) = ( (u32)(value) ) )
+
+
+
+#define rreg16( registerAddress ) \
+ ( *( ( const volatile u16 * )( registerAddress ) ) )
+
+#define wreg16( registerAddress, value ) \
+ ( *( (volatile u16 *)(registerAddress) ) = ( (u16)(value) ) )
+
+#define set_reg_bits16( registerAddress, value ) \
+ ( *( (volatile u16 *)(registerAddress) ) |= ( (u16)(value) ) )
+
+#define clr_reg_bits16( registerAddress, value ) \
+ ( *( (volatile u16 *)(registerAddress) ) &= ( ~( (u16)(value) )
) )
+
+
+#define rreg8( registerAddress ) \
+ ( *( ( const volatile u8 * )( registerAddress ) ) )
+
+#define wreg8( registerAddress, value ) \
+ ( *( (volatile u8 *)(registerAddress) ) = ( (u8)(value) ) )
+
+#define set_reg_bits8( registerAddress, value ) \
+ ( *( (volatile u8 *)(registerAddress) ) |= ( (u8)(value) ) )
+
+#define clr_reg_bits8( registerAddress, value ) \
+ ( *( (volatile u8 *)(registerAddress) ) &= ( ~( (u8)(value) ) )
)
+/* Wait until rINTPND is changed for the case that the ISR is very
short. */
+#endif /*__AS352X_H__*/
diff -urN u-boot-1.1.6.org/include/asm-arm/mach-types.h
u-boot-1.1.6/include/asm-arm/mach-types.h
--- u-boot-1.1.6.org/include/asm-arm/mach-types.h 2006-12-01
17:49:35.000000000 +0800
+++ u-boot-1.1.6/include/asm-arm/mach-types.h 2006-12-01
18:01:45.000000000 +0800
@@ -737,6 +737,7 @@
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
#define MACH_TYPE_PDNB3 1002
+#define MACH_TYPE_AS352X 1166
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -6054,7 +6055,7 @@
# define machine_is_ess710() (0)
#endif
-#ifdef CONFIG_MACH_MX3ADS
+#ifdef CONFIG_MACH_MX31ADS
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
@@ -9401,6 +9402,18 @@
#else
# define machine_is_mp2usb() (0)
#endif
+#ifdef CONFIG_MACH_AS352X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AS352X
+# endif
+# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X)
+#else
+# define machine_is_as352x() (0)
+#endif
+
/*
* These have not yet been registered
diff -urN u-boot-1.1.6.org/include/configs/as352xpb.h
u-boot-1.1.6/include/configs/as352xpb.h
--- u-boot-1.1.6.org/include/configs/as352xpb.h 1970-01-01
08:00:00.000000000 +0800
+++ u-boot-1.1.6/include/configs/as352xpb.h 2006-12-01
17:42:50.000000000 +0800
@@ -0,0 +1,218 @@
+/*
+* (C) Copyright 2006
+* Copyright (C) 2006 Austriamicrosystems, by thomas.luo
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+* High Level Configuration Options
+* (easy to change)
+*/
+#define CONFIG_ARM922T 1 /* This is an ARM922T Core
*/
+#define CONFIG_AS352X 1 /* in a AS352X SoC
*/
+#define CONFIG_AS352XPB 1 /* on a AS352XPB Board
*/
+#define CFG_NO_FLASH 1
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 24000000/* the AS352XPB has 24MHz input
clock */
+
+
+#define USE_922T_MMU 1
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff
*/
+
+/*
+* Size of malloc() pool
+*/
+#define CFG_MALLOC_LEN (((CFG_ENV_SIZE + 128*1024 + 0x4000-1)
/0x4000)*0x4000)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for
initial data */
+
+/*
+* Hardware drivers
+*/
+
+/*
+* select serial console configuration
+*/
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on AS352XPB
*/
+
+/************************************************************
+* RTC
+************************************************************/
+#define CONFIG_RTC_AS352X 0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+/***********************************************************
+* Command definition
+***********************************************************/
+#define CONFIG_COMMANDS \
+ ((CONFIG_CMD_DFL | \
+ /* CFG_CMD_CACHE |*/ \
+ CFG_CMD_NAND | \
+ /*CFG_CMD_EEPROM |*/ \
+ /*CFG_CMD_I2C |*/ \
+ /*CFG_CMD_USB |*/ \
+ CFG_CMD_REGINFO \
+ /*CFG_CMD_ELF*/ )&
~(CFG_CMD_FLASH|CFG_CMD_IMLS|CFG_CMD_NET|CFG_CMD_XIMG))
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if
any) */
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTARGS "root=/dev/ram0 rw init=/linuxrc
console=ttyS0 mem=64M"
+#define CONFIG_BOOTCOMMAND "nand read 0x30007FC0 0x80000 0x200000;
nand read 0x32000000 0x280000 0x200000;bootm 0x30007FC0 0x32000000"
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop
with 's')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR "s"
+/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
+/*#define CONFIG_NETMASK 255.255.255.0*/
+/*#define CONFIG_IPADDR 10.0.0.110*/
+/*#define CONFIG_SERVERIP 10.0.0.1*/
+/*#define CONFIG_BOOTFILE "" */
+/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb
serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to
use */
+#endif
+
+#undef CFG_ENV_IS_IN_FLASH
+/*
+* Miscellaneous configurable options
+*/
+#define CFG_LONGHELP 1 /* undef to save memory
*/
+#define CFG_PROMPT "AS352X # " /* Monitor
Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O
Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print
Buffer Size */
+#define CFG_MAXARGS 8 /* max number of
command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer
Size */
+
+#define CFG_MEMTEST_START 0x30000000 /* memtest works on
*/
+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM
*/
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x30008000 /*
default load address */
+
+#define CFG_HZ 1500000
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_ENV_IS_IN_NAND 1
+
+#define CFG_ENV_NAND_ERASE_SIZE 0x20000
+#define CFG_ENV_SIZE 0x800 /* Total Size of
Environment Sector */
+#if CFG_ENV_IS_IN_NAND
+#define CFG_ENV_OFFSET 0x60000
+
+#endif
+/*---------------------------------------------------------------------
--
+* Stack sizes
+*
+* The stack sizes are set up in start.S using the settings below
+*/
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*---------------------------------------------------------------------
--
+* Physical Memory Map
+*/
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*---------------------------------------------------------------------
--
+* FLASH and environment organization
+*/
+
+#define CONFIG_AMD_LV400 0 /* uncomment this if you have a
LV400 flash */
+#if 0
+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a
LV800 flash */
+#endif
+
+#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one
chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of
environment */
+#endif
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one
chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of
environment */
+#endif
+
+
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices
*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+
+#define NAND_DISABLE_CE(nand) do { } while(0)
+#define NAND_ENABLE_CE(nand) do { } while(0)
+
+#define NAND_WAIT_READY(nand)
+
+#define WRITE_NAND_COMMAND(d, adr) do{ } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ } while(0)
+#define WRITE_NAND(d, adr) do{} while(0)
+#define READ_NAND(adr) ()
+/* the following are NOP's in our implementation */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash
Erase */
+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash
Write */
+
+
+
+
+
+
+#include <as352x.h>
+#define CFG_NAND_BASE NAF_DATA
+#include <cmd_confdefs.h>
+
+#define NAND_ALLOW_ERASE_ALL
+
+
+
+#endif /* __CONFIG_H */
diff -urN u-boot-1.1.6.org/MAINTAINERS u-boot-1.1.6/MAINTAINERS
--- u-boot-1.1.6.org/MAINTAINERS 2006-12-01 17:49:32.000000000
+0800
+++ u-boot-1.1.6/MAINTAINERS 2006-11-30 09:40:51.000000000 +0800
@@ -566,6 +566,17 @@
Haavard Skinnemoen <hskinnemoen at atmel.com>
ATSTK1000 AT32AP7000
+#######################################################################
##
+# AS352X Systems:
#
+#
#
+# Maintainer Name, Email Address
#
+# Board CPU
#
+#######################################################################
##
+
+Thomas Luo <thomas.luo at austriamicrosystems.com>
+
+ AS352XPB AS352X
+
########################################################################
#
# End of MAINTAINERS list
#
diff -urN u-boot-1.1.6.org/MAKEALL u-boot-1.1.6/MAKEALL
--- u-boot-1.1.6.org/MAKEALL 2006-12-01 17:49:32.000000000 +0800
+++ u-boot-1.1.6/MAKEALL 2006-11-30 09:33:22.000000000 +0800
@@ -189,13 +189,13 @@
LIST_ARM9=" \
at91rm9200dk cmc_pu2
\
ap920t ap922_XA10 ap926ejs ap946es
\
- ap966 cp920t cp922_XA10 cp926ejs
\
+ ap966 cp920t cp922t cp922_XA10 cp926ejs
\
cp946es cp966 lpd7a400 mp2usb
\
mx1ads mx1fs2 netstar omap1510inn
\
omap1610h2 omap1610inn omap730p2 sbc2410x
\
scb9328 smdk2400 smdk2410 trab
\
VCMA9 versatile versatileab versatilepb
\
- voiceblue
\
+ voiceblue as3525pb
\
"
########################################################################
#
diff -urN u-boot-1.1.6.org/Makefile u-boot-1.1.6/Makefile
--- u-boot-1.1.6.org/Makefile 2006-12-01 17:49:33.000000000 +0800
+++ u-boot-1.1.6/Makefile 2006-11-30 09:38:22.000000000 +0800
@@ -2253,6 +2253,9 @@
@./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel
at32ap7000
########################################################################
#
+as352xpb_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm922t as352xpb NULL as352x
+
########################################################################
#
########################################################################
#
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