[U-Boot-Users] [ARM] TI DaVinci support, hopefully final [4/5]
Dirk Behme
dirk.behme at googlemail.com
Wed Aug 8 17:58:22 CEST 2007
ksi at koi8.net wrote:
> Signed-off-by: Sergey Kubushyn <ksi at koi8.net>
Acked-by: Dirk Behme <dirk.behme at gmail.com>
> diff -purN u-boot.git.orig/include/asm-arm/arch-davinci/emac_defs.h u-boot.git/include/asm-arm/arch-davinci/emac_defs.h
> --- u-boot.git.orig/include/asm-arm/arch-davinci/emac_defs.h 1969-12-31 16:00:00.000000000 -0800
> +++ u-boot.git/include/asm-arm/arch-davinci/emac_defs.h 2007-08-07 10:15:34.000000000 -0700
> @@ -0,0 +1,311 @@
> +/*
> + * Copyright (C) 2007 Sergey Kubushyn <ksi at koi8.net>
> + *
> + * Based on:
> + *
> + * ----------------------------------------------------------------------------
> + *
> + * dm644x_emac.h
> + *
> + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
> + *
> + * Copyright (C) 2005 Texas Instruments.
> + *
> + * ----------------------------------------------------------------------------
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + * ----------------------------------------------------------------------------
> +
> + * Modifications:
> + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
> + *
> + */
> +
> +#ifndef _DM644X_EMAC_H_
> +#define _DM644X_EMAC_H_
> +
> +#include <asm/arch/hardware.h>
> +
> +#define EMAC_BASE_ADDR (0x01c80000)
> +#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
> +#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
> +#define EMAC_MDIO_BASE_ADDR (0x01c84000)
> +
> +/* MDIO module input frequency */
> +#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
> +/* MDIO clock output frequency */
> +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
> +
> +/* Ethernet Min/Max packet size */
> +#define EMAC_MIN_ETHERNET_PKT_SIZE 60
> +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
> +#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
> +
> +/* Number of RX packet buffers
> + * NOTE: Only 1 buffer supported as of now
> + */
> +#define EMAC_MAX_RX_BUFFERS 10
> +
> +
> +/***********************************************
> + ******** Internally used macros ***************
> + ***********************************************/
> +
> +#define EMAC_CH_TX 1
> +#define EMAC_CH_RX 0
> +
> +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
> + * reserve space for 64 descriptors max
> + */
> +#define EMAC_RX_DESC_BASE 0x0
> +#define EMAC_TX_DESC_BASE 0x1000
> +
> +/* EMAC Teardown value */
> +#define EMAC_TEARDOWN_VALUE 0xfffffffc
> +
> +/* MII Status Register */
> +#define MII_STATUS_REG 1
> +
> +/* Number of statistics registers */
> +#define EMAC_NUM_STATS 36
> +
> +
> +/* EMAC Descriptor */
> +typedef volatile struct _emac_desc
> +{
> + u_int32_t next; /* Pointer to next descriptor in chain */
> + u_int8_t *buffer; /* Pointer to data buffer */
> + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
> + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
> +} emac_desc;
> +
> +/* CPPI bit positions */
> +#define EMAC_CPPI_SOP_BIT (0x80000000)
> +#define EMAC_CPPI_EOP_BIT (0x40000000)
> +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
> +#define EMAC_CPPI_EOQ_BIT (0x10000000)
> +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
> +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
> +
> +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
> +
> +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
> +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
> +
> +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
> +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
> +
> +
> +#define MDIO_CONTROL_IDLE (0x80000000)
> +#define MDIO_CONTROL_ENABLE (0x40000000)
> +#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
> +#define MDIO_CONTROL_FAULT (0x80000)
> +#define MDIO_USERACCESS0_GO (0x80000000)
> +#define MDIO_USERACCESS0_WRITE_READ (0x0)
> +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
> +#define MDIO_USERACCESS0_ACK (0x20000000)
> +
> +/* Ethernet MAC Registers Structure */
> +typedef struct {
> + dv_reg TXIDVER;
> + dv_reg TXCONTROL;
> + dv_reg TXTEARDOWN;
> + u_int8_t RSVD0[4];
> + dv_reg RXIDVER;
> + dv_reg RXCONTROL;
> + dv_reg RXTEARDOWN;
> + u_int8_t RSVD1[100];
> + dv_reg TXINTSTATRAW;
> + dv_reg TXINTSTATMASKED;
> + dv_reg TXINTMASKSET;
> + dv_reg TXINTMASKCLEAR;
> + dv_reg MACINVECTOR;
> + u_int8_t RSVD2[12];
> + dv_reg RXINTSTATRAW;
> + dv_reg RXINTSTATMASKED;
> + dv_reg RXINTMASKSET;
> + dv_reg RXINTMASKCLEAR;
> + dv_reg MACINTSTATRAW;
> + dv_reg MACINTSTATMASKED;
> + dv_reg MACINTMASKSET;
> + dv_reg MACINTMASKCLEAR;
> + u_int8_t RSVD3[64];
> + dv_reg RXMBPENABLE;
> + dv_reg RXUNICASTSET;
> + dv_reg RXUNICASTCLEAR;
> + dv_reg RXMAXLEN;
> + dv_reg RXBUFFEROFFSET;
> + dv_reg RXFILTERLOWTHRESH;
> + u_int8_t RSVD4[8];
> + dv_reg RX0FLOWTHRESH;
> + dv_reg RX1FLOWTHRESH;
> + dv_reg RX2FLOWTHRESH;
> + dv_reg RX3FLOWTHRESH;
> + dv_reg RX4FLOWTHRESH;
> + dv_reg RX5FLOWTHRESH;
> + dv_reg RX6FLOWTHRESH;
> + dv_reg RX7FLOWTHRESH;
> + dv_reg RX0FREEBUFFER;
> + dv_reg RX1FREEBUFFER;
> + dv_reg RX2FREEBUFFER;
> + dv_reg RX3FREEBUFFER;
> + dv_reg RX4FREEBUFFER;
> + dv_reg RX5FREEBUFFER;
> + dv_reg RX6FREEBUFFER;
> + dv_reg RX7FREEBUFFER;
> + dv_reg MACCONTROL;
> + dv_reg MACSTATUS;
> + dv_reg EMCONTROL;
> + dv_reg FIFOCONTROL;
> + dv_reg MACCONFIG;
> + dv_reg SOFTRESET;
> + u_int8_t RSVD5[88];
> + dv_reg MACSRCADDRLO;
> + dv_reg MACSRCADDRHI;
> + dv_reg MACHASH1;
> + dv_reg MACHASH2;
> + dv_reg BOFFTEST;
> + dv_reg TPACETEST;
> + dv_reg RXPAUSE;
> + dv_reg TXPAUSE;
> + u_int8_t RSVD6[16];
> + dv_reg RXGOODFRAMES;
> + dv_reg RXBCASTFRAMES;
> + dv_reg RXMCASTFRAMES;
> + dv_reg RXPAUSEFRAMES;
> + dv_reg RXCRCERRORS;
> + dv_reg RXALIGNCODEERRORS;
> + dv_reg RXOVERSIZED;
> + dv_reg RXJABBER;
> + dv_reg RXUNDERSIZED;
> + dv_reg RXFRAGMENTS;
> + dv_reg RXFILTERED;
> + dv_reg RXQOSFILTERED;
> + dv_reg RXOCTETS;
> + dv_reg TXGOODFRAMES;
> + dv_reg TXBCASTFRAMES;
> + dv_reg TXMCASTFRAMES;
> + dv_reg TXPAUSEFRAMES;
> + dv_reg TXDEFERRED;
> + dv_reg TXCOLLISION;
> + dv_reg TXSINGLECOLL;
> + dv_reg TXMULTICOLL;
> + dv_reg TXEXCESSIVECOLL;
> + dv_reg TXLATECOLL;
> + dv_reg TXUNDERRUN;
> + dv_reg TXCARRIERSENSE;
> + dv_reg TXOCTETS;
> + dv_reg FRAME64;
> + dv_reg FRAME65T127;
> + dv_reg FRAME128T255;
> + dv_reg FRAME256T511;
> + dv_reg FRAME512T1023;
> + dv_reg FRAME1024TUP;
> + dv_reg NETOCTETS;
> + dv_reg RXSOFOVERRUNS;
> + dv_reg RXMOFOVERRUNS;
> + dv_reg RXDMAOVERRUNS;
> + u_int8_t RSVD7[624];
> + dv_reg MACADDRLO;
> + dv_reg MACADDRHI;
> + dv_reg MACINDEX;
> + u_int8_t RSVD8[244];
> + dv_reg TX0HDP;
> + dv_reg TX1HDP;
> + dv_reg TX2HDP;
> + dv_reg TX3HDP;
> + dv_reg TX4HDP;
> + dv_reg TX5HDP;
> + dv_reg TX6HDP;
> + dv_reg TX7HDP;
> + dv_reg RX0HDP;
> + dv_reg RX1HDP;
> + dv_reg RX2HDP;
> + dv_reg RX3HDP;
> + dv_reg RX4HDP;
> + dv_reg RX5HDP;
> + dv_reg RX6HDP;
> + dv_reg RX7HDP;
> + dv_reg TX0CP;
> + dv_reg TX1CP;
> + dv_reg TX2CP;
> + dv_reg TX3CP;
> + dv_reg TX4CP;
> + dv_reg TX5CP;
> + dv_reg TX6CP;
> + dv_reg TX7CP;
> + dv_reg RX0CP;
> + dv_reg RX1CP;
> + dv_reg RX2CP;
> + dv_reg RX3CP;
> + dv_reg RX4CP;
> + dv_reg RX5CP;
> + dv_reg RX6CP;
> + dv_reg RX7CP;
> +} emac_regs;
> +
> +/* EMAC Wrapper Registers Structure */
> +typedef struct {
> + u_int8_t RSVD0[4100];
> + dv_reg EWCTL;
> + dv_reg EWINTTCNT;
> +} ewrap_regs;
> +
> +
> +/* EMAC MDIO Registers Structure */
> +typedef struct {
> + dv_reg VERSION;
> + dv_reg CONTROL;
> + dv_reg ALIVE;
> + dv_reg LINK;
> + dv_reg LINKINTRAW;
> + dv_reg LINKINTMASKED;
> + u_int8_t RSVD0[8];
> + dv_reg USERINTRAW;
> + dv_reg USERINTMASKED;
> + dv_reg USERINTMASKSET;
> + dv_reg USERINTMASKCLEAR;
> + u_int8_t RSVD1[80];
> + dv_reg USERACCESS0;
> + dv_reg USERPHYSEL0;
> + dv_reg USERACCESS1;
> + dv_reg USERPHYSEL1;
> +} mdio_regs;
> +
> +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
> +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
> +
> +typedef struct
> +{
> + char name[64];
> + int (*init)(int phy_addr);
> + int (*is_phy_connected)(int phy_addr);
> + int (*get_link_speed)(int phy_addr);
> + int (*auto_negotiate)(int phy_addr);
> +} phy_t;
> +
> +#define PHY_LXT972 (0x001378e2)
> +int lxt972_is_phy_connected(int phy_addr);
> +int lxt972_get_link_speed(int phy_addr);
> +int lxt972_init_phy(int phy_addr);
> +int lxt972_auto_negotiate(int phy_addr);
> +
> +#define PHY_DP83848 (0x20005c90)
> +int dp83848_is_phy_connected(int phy_addr);
> +int dp83848_get_link_speed(int phy_addr);
> +int dp83848_init_phy(int phy_addr);
> +int dp83848_auto_negotiate(int phy_addr);
> +
> +#endif /* _DM644X_EMAC_H_ */
> diff -purN u-boot.git.orig/include/asm-arm/arch-davinci/emif_defs.h u-boot.git/include/asm-arm/arch-davinci/emif_defs.h
> --- u-boot.git.orig/include/asm-arm/arch-davinci/emif_defs.h 1969-12-31 16:00:00.000000000 -0800
> +++ u-boot.git/include/asm-arm/arch-davinci/emif_defs.h 2007-08-07 10:15:34.000000000 -0700
> @@ -0,0 +1,61 @@
> +/*
> + * Copyright (C) 2007 Sergey Kubushyn <ksi at koi8.net>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _EMIF_DEFS_H_
> +#define _EMIF_DEFS_H_
> +
> +#include <asm/arch/hardware.h>
> +
> +typedef struct {
> + dv_reg ERCSR;
> + dv_reg AWCCR;
> + dv_reg SDBCR;
> + dv_reg SDRCR;
> + dv_reg AB1CR;
> + dv_reg AB2CR;
> + dv_reg AB3CR;
> + dv_reg AB4CR;
> + dv_reg SDTIMR;
> + dv_reg DDRSR;
> + dv_reg DDRPHYCR;
> + dv_reg DDRPHYSR;
> + dv_reg TOTAR;
> + dv_reg TOTACTR;
> + dv_reg DDRPHYID_REV;
> + dv_reg SDSRETR;
> + dv_reg EIRR;
> + dv_reg EIMR;
> + dv_reg EIMSR;
> + dv_reg EIMCR;
> + dv_reg IOCTRLR;
> + dv_reg IOSTATR;
> + u_int8_t RSVD0[8];
> + dv_reg NANDFCR;
> + dv_reg NANDFSR;
> + u_int8_t RSVD1[8];
> + dv_reg NANDF1ECC;
> + dv_reg NANDF2ECC;
> + dv_reg NANDF3ECC;
> + dv_reg NANDF4ECC;
> +} emif_registers;
> +
> +typedef emif_registers *emifregs;
> +#endif
> diff -purN u-boot.git.orig/include/asm-arm/arch-davinci/hardware.h u-boot.git/include/asm-arm/arch-davinci/hardware.h
> --- u-boot.git.orig/include/asm-arm/arch-davinci/hardware.h 1969-12-31 16:00:00.000000000 -0800
> +++ u-boot.git/include/asm-arm/arch-davinci/hardware.h 2007-08-07 10:15:34.000000000 -0700
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (C) 2007 Sergey Kubushyn <ksi at koi8.net>
> + *
> + * Based on:
> + *
> + * -------------------------------------------------------------------------
> + *
> + * linux/include/asm-arm/arch-davinci/hardware.h
> + *
> + * Copyright (C) 2006 Texas Instruments.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
> + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
> + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
> + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + *
> + */
> +#ifndef __ASM_ARCH_HARDWARE_H
> +#define __ASM_ARCH_HARDWARE_H
> +
> +#include <config.h>
> +#include <asm/sizes.h>
> +
> +#define REG(addr) (*(volatile unsigned int *)(addr))
> +#define REG_P(addr) ((volatile unsigned int *)(addr))
> +
> +typedef volatile unsigned int dv_reg;
> +typedef volatile unsigned int * dv_reg_p;
> +
> +/*
> + * Base register addresses
> + */
> +#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
> +#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
> +#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
> +#define DAVINCI_UART0_BASE (0x01c20000)
> +#define DAVINCI_UART1_BASE (0x01c20400)
> +#define DAVINCI_UART2_BASE (0x01c20800)
> +#define DAVINCI_I2C_BASE (0x01c21000)
> +#define DAVINCI_TIMER0_BASE (0x01c21400)
> +#define DAVINCI_TIMER1_BASE (0x01c21800)
> +#define DAVINCI_WDOG_BASE (0x01c21c00)
> +#define DAVINCI_PWM0_BASE (0x01c22000)
> +#define DAVINCI_PWM1_BASE (0x01c22400)
> +#define DAVINCI_PWM2_BASE (0x01c22800)
> +#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
> +#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
> +#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
> +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
> +#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000)
> +#define DAVINCI_ARM_INTC_BASE (0x01c48000)
> +#define DAVINCI_IEEE1394_BASE (0x01c60000)
> +#define DAVINCI_USB_OTG_BASE (0x01c64000)
> +#define DAVINCI_CFC_ATA_BASE (0x01c66000)
> +#define DAVINCI_SPI_BASE (0x01c66800)
> +#define DAVINCI_GPIO_BASE (0x01c67000)
> +#define DAVINCI_UHPI_BASE (0x01c67800)
> +#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
> +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000)
> +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000)
> +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000)
> +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000)
> +#define DAVINCI_IMCOP_BASE (0x01cc0000)
> +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000)
> +#define DAVINCI_VLYNQ_BASE (0x01e01000)
> +#define DAVINCI_MCBSP_BASE (0x01e02000)
> +#define DAVINCI_MMC_SD_BASE (0x01e10000)
> +#define DAVINCI_MS_BASE (0x01e20000)
> +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
> +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
> +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
> +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
> +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000)
> +
> +/* Power and Sleep Controller (PSC) Domains */
> +#define DAVINCI_GPSC_ARMDOMAIN 0
> +#define DAVINCI_GPSC_DSPDOMAIN 1
> +
> +#define DAVINCI_LPSC_VPSSMSTR 0
> +#define DAVINCI_LPSC_VPSSSLV 1
> +#define DAVINCI_LPSC_TPCC 2
> +#define DAVINCI_LPSC_TPTC0 3
> +#define DAVINCI_LPSC_TPTC1 4
> +#define DAVINCI_LPSC_EMAC 5
> +#define DAVINCI_LPSC_EMAC_WRAPPER 6
> +#define DAVINCI_LPSC_MDIO 7
> +#define DAVINCI_LPSC_IEEE1394 8
> +#define DAVINCI_LPSC_USB 9
> +#define DAVINCI_LPSC_ATA 10
> +#define DAVINCI_LPSC_VLYNQ 11
> +#define DAVINCI_LPSC_UHPI 12
> +#define DAVINCI_LPSC_DDR_EMIF 13
> +#define DAVINCI_LPSC_AEMIF 14
> +#define DAVINCI_LPSC_MMC_SD 15
> +#define DAVINCI_LPSC_MEMSTICK 16
> +#define DAVINCI_LPSC_McBSP 17
> +#define DAVINCI_LPSC_I2C 18
> +#define DAVINCI_LPSC_UART0 19
> +#define DAVINCI_LPSC_UART1 20
> +#define DAVINCI_LPSC_UART2 21
> +#define DAVINCI_LPSC_SPI 22
> +#define DAVINCI_LPSC_PWM0 23
> +#define DAVINCI_LPSC_PWM1 24
> +#define DAVINCI_LPSC_PWM2 25
> +#define DAVINCI_LPSC_GPIO 26
> +#define DAVINCI_LPSC_TIMER0 27
> +#define DAVINCI_LPSC_TIMER1 28
> +#define DAVINCI_LPSC_TIMER2 29
> +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
> +#define DAVINCI_LPSC_ARM 31
> +#define DAVINCI_LPSC_SCR2 32
> +#define DAVINCI_LPSC_SCR3 33
> +#define DAVINCI_LPSC_SCR4 34
> +#define DAVINCI_LPSC_CROSSBAR 35
> +#define DAVINCI_LPSC_CFG27 36
> +#define DAVINCI_LPSC_CFG3 37
> +#define DAVINCI_LPSC_CFG5 38
> +#define DAVINCI_LPSC_GEM 39
> +#define DAVINCI_LPSC_IMCOP 40
> +
> +/* Some PSC defines */
> +#define PSC_CHP_SHRTSW (0x01c40038)
> +#define PSC_GBLCTL (0x01c41010)
> +#define PSC_EPCPR (0x01c41070)
> +#define PSC_EPCCR (0x01c41078)
> +#define PSC_PTCMD (0x01c41120)
> +#define PSC_PTSTAT (0x01c41128)
> +#define PSC_PDSTAT (0x01c41200)
> +#define PSC_PDSTAT1 (0x01c41204)
> +#define PSC_PDCTL (0x01c41300)
> +#define PSC_PDCTL1 (0x01c41304)
> +
> +#define PSC_MDCTL_BASE (0x01c41a00)
> +#define PSC_MDSTAT_BASE (0x01c41800)
> +
> +#define VDD3P3V_PWDN (0x01c40048)
> +#define UART0_PWREMU_MGMT (0x01c20030)
> +
> +#define PSC_SILVER_BULLET (0x01c41a20)
> +
> +/* Some PLL defines */
> +#define PLL1_PLLM (0x01c40910)
> +#define PLL2_PLLM (0x01c40d10)
> +#define PLL2_DIV2 (0x01c40d1c)
> +
> +/* Miscellania... */
> +#define VBPR (0x20000020)
> +#define PINMUX0 (0x01c40000)
> +#define PINMUX1 (0x01c40004)
> +
> +#endif /* __ASM_ARCH_HARDWARE_H */
> diff -purN u-boot.git.orig/include/asm-arm/arch-davinci/i2c_defs.h u-boot.git/include/asm-arm/arch-davinci/i2c_defs.h
> --- u-boot.git.orig/include/asm-arm/arch-davinci/i2c_defs.h 1969-12-31 16:00:00.000000000 -0800
> +++ u-boot.git/include/asm-arm/arch-davinci/i2c_defs.h 2007-08-07 10:15:34.000000000 -0700
> @@ -0,0 +1,94 @@
> +/*
> + * (C) Copyright 2004
> + * Texas Instruments, <www.ti.com>
> + *
> + * Some changes copyright (C) 2007 Sergey Kubushyn <ksi at koi8.net>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _DAVINCI_I2C_H_
> +#define _DAVINCI_I2C_H_
> +
> +#define I2C_WRITE 0
> +#define I2C_READ 1
> +
> +#define I2C_BASE 0x01c21000
> +
> +#define I2C_OA (I2C_BASE + 0x00)
> +#define I2C_IE (I2C_BASE + 0x04)
> +#define I2C_STAT (I2C_BASE + 0x08)
> +#define I2C_SCLL (I2C_BASE + 0x0c)
> +#define I2C_SCLH (I2C_BASE + 0x10)
> +#define I2C_CNT (I2C_BASE + 0x14)
> +#define I2C_DRR (I2C_BASE + 0x18)
> +#define I2C_SA (I2C_BASE + 0x1c)
> +#define I2C_DXR (I2C_BASE + 0x20)
> +#define I2C_CON (I2C_BASE + 0x24)
> +#define I2C_IV (I2C_BASE + 0x28)
> +#define I2C_PSC (I2C_BASE + 0x30)
> +
> +/* I2C masks */
> +
> +/* I2C Interrupt Enable Register (I2C_IE): */
> +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
> +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
> +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
> +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
> +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
> +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
> +
> +/* I2C Status Register (I2C_STAT): */
> +
> +#define I2C_STAT_BB (1 << 12) /* Bus busy */
> +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
> +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
> +#define I2C_STAT_AAS (1 << 9) /* Address as slave */
> +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
> +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
> +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
> +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
> +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
> +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
> +
> +
> +/* I2C Interrupt Code Register (I2C_INTCODE): */
> +
> +#define I2C_INTCODE_MASK 7
> +#define I2C_INTCODE_NONE 0
> +#define I2C_INTCODE_AL 1 /* Arbitration lost */
> +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
> +#define I2C_INTCODE_ARDY 3 /* Register access ready */
> +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
> +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
> +#define I2C_INTCODE_SCD 6 /* Stop condition detect */
> +
> +
> +/* I2C Configuration Register (I2C_CON): */
> +
> +#define I2C_CON_EN (1 << 5) /* I2C module enable */
> +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
> +#define I2C_CON_MST (1 << 10) /* Master/slave mode */
> +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
> +#define I2C_CON_XA (1 << 8) /* Expand address */
> +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
> +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
> +
> +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
> +
> +#endif
> diff -purN u-boot.git.orig/include/asm-arm/arch-davinci/nand_defs.h u-boot.git/include/asm-arm/arch-davinci/nand_defs.h
> --- u-boot.git.orig/include/asm-arm/arch-davinci/nand_defs.h 1969-12-31 16:00:00.000000000 -0800
> +++ u-boot.git/include/asm-arm/arch-davinci/nand_defs.h 2007-08-07 10:15:34.000000000 -0700
> @@ -0,0 +1,161 @@
> +/*
> + * Copyright (C) 2007 Sergey Kubushyn <ksi at koi8.net>
> + *
> + * Parts shamelesly stolen from Linux Kernel source tree.
> + *
> + * ------------------------------------------------------------
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _NAND_DEFS_H_
> +#define _NAND_DEFS_H_
> +
> +#include <asm/arch/hardware.h>
> +
> +#define MASK_CLE 0x10
> +#define MASK_ALE 0x0a
> +
> +#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
> +#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
> +#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE)
> +
> +typedef struct {
> + u_int32_t NRCSR;
> + u_int32_t AWCCR;
> + u_int8_t RSVD0[8];
> + u_int32_t AB1CR;
> + u_int32_t AB2CR;
> + u_int32_t AB3CR;
> + u_int32_t AB4CR;
> + u_int8_t RSVD1[32];
> + u_int32_t NIRR;
> + u_int32_t NIMR;
> + u_int32_t NIMSR;
> + u_int32_t NIMCR;
> + u_int8_t RSVD2[16];
> + u_int32_t NANDFCR;
> + u_int32_t NANDFSR;
> + u_int8_t RSVD3[8];
> + u_int32_t NANDF1ECC;
> + u_int32_t NANDF2ECC;
> + u_int32_t NANDF3ECC;
> + u_int32_t NANDF4ECC;
> + u_int8_t RSVD4[4];
> + u_int32_t IODFTECR;
> + u_int32_t IODFTGCR;
> + u_int8_t RSVD5[4];
> + u_int32_t IODFTMRLR;
> + u_int32_t IODFTMRMR;
> + u_int32_t IODFTMRMSBR;
> + u_int8_t RSVD6[20];
> + u_int32_t MODRNR;
> + u_int8_t RSVD7[76];
> + u_int32_t CE0DATA;
> + u_int32_t CE0ALE;
> + u_int32_t CE0CLE;
> + u_int8_t RSVD8[4];
> + u_int32_t CE1DATA;
> + u_int32_t CE1ALE;
> + u_int32_t CE1CLE;
> + u_int8_t RSVD9[4];
> + u_int32_t CE2DATA;
> + u_int32_t CE2ALE;
> + u_int32_t CE2CLE;
> + u_int8_t RSVD10[4];
> + u_int32_t CE3DATA;
> + u_int32_t CE3ALE;
> + u_int32_t CE3CLE;
> +} nand_registers;
> +
> +typedef volatile nand_registers *nandregs;
> +
> +#define NAND_READ_START 0x00
> +#define NAND_READ_END 0x30
> +#define NAND_STATUS 0x70
> +
> +#ifdef CFG_NAND_HW_ECC
> +#define NAND_Ecc_P1e (1 << 0)
> +#define NAND_Ecc_P2e (1 << 1)
> +#define NAND_Ecc_P4e (1 << 2)
> +#define NAND_Ecc_P8e (1 << 3)
> +#define NAND_Ecc_P16e (1 << 4)
> +#define NAND_Ecc_P32e (1 << 5)
> +#define NAND_Ecc_P64e (1 << 6)
> +#define NAND_Ecc_P128e (1 << 7)
> +#define NAND_Ecc_P256e (1 << 8)
> +#define NAND_Ecc_P512e (1 << 9)
> +#define NAND_Ecc_P1024e (1 << 10)
> +#define NAND_Ecc_P2048e (1 << 11)
> +
> +#define NAND_Ecc_P1o (1 << 16)
> +#define NAND_Ecc_P2o (1 << 17)
> +#define NAND_Ecc_P4o (1 << 18)
> +#define NAND_Ecc_P8o (1 << 19)
> +#define NAND_Ecc_P16o (1 << 20)
> +#define NAND_Ecc_P32o (1 << 21)
> +#define NAND_Ecc_P64o (1 << 22)
> +#define NAND_Ecc_P128o (1 << 23)
> +#define NAND_Ecc_P256o (1 << 24)
> +#define NAND_Ecc_P512o (1 << 25)
> +#define NAND_Ecc_P1024o (1 << 26)
> +#define NAND_Ecc_P2048o (1 << 27)
> +
> +#define TF(v) (v ? 1 : 0)
> +
> +#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
> +#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
> +#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
> +#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
> +#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
> +#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
> +#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
> +#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
> +
> +#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
> +#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
> +#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
> +#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
> +#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
> +#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
> +#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
> +#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
> +
> +#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
> +#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
> +#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
> +#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
> +#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
> +#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
> +#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
> +#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
> +
> +#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
> +#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
> +#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
> +#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
> +#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
> +#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
> +#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
> +#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
> +
> +#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
> +#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
> +#endif
> +
> +#endif
> diff -purN u-boot.git.orig/include/common.h u-boot.git/include/common.h
> --- u-boot.git.orig/include/common.h 2007-08-06 18:05:59.000000000 -0700
> +++ u-boot.git/include/common.h 2007-08-07 10:15:34.000000000 -0700
> @@ -241,6 +241,9 @@ int saveenv (void);
> void inline setenv (char *, char *);
> #else
> void setenv (char *, char *);
> +#ifdef CONFIG_HAS_UID
> +void forceenv (char *, char *);
> +#endif
> #endif /* CONFIG_PPC */
> #ifdef CONFIG_ARM
> # include <asm/mach-types.h>
> diff -purN u-boot.git.orig/include/dp83848.h u-boot.git/include/dp83848.h
> --- u-boot.git.orig/include/dp83848.h 1969-12-31 16:00:00.000000000 -0800
> +++ u-boot.git/include/dp83848.h 2007-08-07 10:15:34.000000000 -0700
> @@ -0,0 +1,88 @@
> +/*
> + * DP83848 ethernet Physical layer
> + *
> + * Copyright (C) 2007 Sergey Kubushyn <ksi at koi8.net>
> + *
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +
> +/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
> +
> +#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
> +#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
> +#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
> +#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
> +#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
> +#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
> +#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
> +#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
> +#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
> +#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
> +
> +/*--Bit definitions: DP83848_CTL_REG */
> +#define DP83848_RESET (1 << 15) /* 1= S/W Reset */
> +#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
> +#define DP83848_SPEED_SELECT (1 << 13)
> +#define DP83848_AUTONEG (1 << 12)
> +#define DP83848_POWER_DOWN (1 << 11)
> +#define DP83848_ISOLATE (1 << 10)
> +#define DP83848_RESTART_AUTONEG (1 << 9)
> +#define DP83848_DUPLEX_MODE (1 << 8)
> +#define DP83848_COLLISION_TEST (1 << 7)
> +
> +/*--Bit definitions: DP83848_STAT_REG */
> +#define DP83848_100BASE_T4 (1 << 15)
> +#define DP83848_100BASE_TX_FD (1 << 14)
> +#define DP83848_100BASE_TX_HD (1 << 13)
> +#define DP83848_10BASE_T_FD (1 << 12)
> +#define DP83848_10BASE_T_HD (1 << 11)
> +#define DP83848_MF_PREAMB_SUPPR (1 << 6)
> +#define DP83848_AUTONEG_COMP (1 << 5)
> +#define DP83848_RMT_FAULT (1 << 4)
> +#define DP83848_AUTONEG_ABILITY (1 << 3)
> +#define DP83848_LINK_STATUS (1 << 2)
> +#define DP83848_JABBER_DETECT (1 << 1)
> +#define DP83848_EXTEND_CAPAB (1 << 0)
> +
> +/*--definitions: DP83848_PHYID1 */
> +#define DP83848_PHYID1_OUI 0x2000
> +#define DP83848_PHYID2_OUI 0x5c90
> +
> +/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
> +#define DP83848_NP (1 << 15)
> +#define DP83848_ACK (1 << 14)
> +#define DP83848_RF (1 << 13)
> +#define DP83848_PAUSE (1 << 10)
> +#define DP83848_T4 (1 << 9)
> +#define DP83848_TX_FDX (1 << 8)
> +#define DP83848_TX_HDX (1 << 7)
> +#define DP83848_10_FDX (1 << 6)
> +#define DP83848_10_HDX (1 << 5)
> +#define DP83848_AN_IEEE_802_3 0x0001
> +
> +/*--Bit definitions: DP83848_ANER */
> +#define DP83848_PDF (1 << 4)
> +#define DP83848_LP_NP_ABLE (1 << 3)
> +#define DP83848_NP_ABLE (1 << 2)
> +#define DP83848_PAGE_RX (1 << 1)
> +#define DP83848_LP_AN_ABLE (1 << 0)
> +
> +/*--Bit definitions: DP83848_PHY_STAT */
> +#define DP83848_RX_ERR_LATCH (1 << 13)
> +#define DP83848_POLARITY_STAT (1 << 12)
> +#define DP83848_FALSE_CAR_SENSE (1 << 11)
> +#define DP83848_SIG_DETECT (1 << 10)
> +#define DP83848_DESCRAM_LOCK (1 << 9)
> +#define DP83848_PAGE_RCV (1 << 8)
> +#define DP83848_PHY_RMT_FAULT (1 << 6)
> +#define DP83848_JABBER (1 << 5)
> +#define DP83848_AUTONEG_COMPLETE (1 << 4)
> +#define DP83848_LOOPBACK_STAT (1 << 3)
> +#define DP83848_DUPLEX (1 << 2)
> +#define DP83848_SPEED (1 << 1)
> +#define DP83848_LINK (1 << 0)
> diff -purN u-boot.git.orig/include/_exports.h u-boot.git/include/_exports.h
> --- u-boot.git.orig/include/_exports.h 2007-08-06 18:05:59.000000000 -0700
> +++ u-boot.git/include/_exports.h 2007-08-07 10:15:34.000000000 -0700
> @@ -14,6 +14,9 @@ EXPORT_FUNC(vprintf)
> EXPORT_FUNC(do_reset)
> EXPORT_FUNC(getenv)
> EXPORT_FUNC(setenv)
> +#ifdef CONFIG_HAS_UID
> +EXPORT_FUNC(forceenv)
> +#endif
> EXPORT_FUNC(simple_strtoul)
> EXPORT_FUNC(simple_strtol)
> EXPORT_FUNC(strcmp)
> diff -purN u-boot.git.orig/include/exports.h u-boot.git/include/exports.h
> --- u-boot.git.orig/include/exports.h 2007-08-06 18:05:59.000000000 -0700
> +++ u-boot.git/include/exports.h 2007-08-07 10:15:34.000000000 -0700
> @@ -25,6 +25,9 @@ char *getenv (char *name);
> void setenv (char *varname, char *varvalue);
> long simple_strtol(const char *cp,char **endp,unsigned int base);
> int strcmp(const char * cs,const char * ct);
> +#ifdef CONFIG_HAS_UID
> +void forceenv (char *varname, char *varvalue);
> +#endif
> #if defined(CONFIG_CMD_I2C)
> int i2c_write (uchar, uint, int , uchar* , int);
> int i2c_read (uchar, uint, int , uchar* , int);
>
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