[U-Boot-Users] [PATCH] Fix MPC8544DS PCIe3 scsi.
Ed Swarthout
ed.swarthout at hwdebug.com
Mon Aug 20 10:03:51 CEST 2007
From: Ed Swarthout <ed.swarthout at freescale.com>
Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:
SCSI: scanning bus for devices...
Invaild port number 1
Invaild port number 2
Invaild port number 3
Signed-off-by: Ed Swarthout <ed.swarthout at freescale.com>
---
d64ee908 reduced PCIe 3 region by too much.
With this fix I get 0xb010c000 assigned to bar5.
board/freescale/mpc8544ds/init.S | 2 +-
include/configs/MPC8544DS.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 900c368..ca1b5d5 100644
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -237,6 +237,6 @@ law_entry:
/* contains both PCIE3 MEM & IO space */
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
+ .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
4:
entry_end
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 746f360..ba5aa00 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -308,9 +308,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE 0xb0000000
#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE3_MEM_SIZE 0x00800000 /* 8M of 16M LAW */
#define CFG_PCIE3_IO_BASE 0x00000000
-#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
+#define CFG_PCIE3_IO_PHYS 0xb0800000 /* reuse mem LAW */
#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
--
1.5.3.rc5.18.ga85e4
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