[U-Boot-Users] [PATCH 1/3 RESEND] ppc4xx: Add initial esd PMC440 board files

Matthias Fuchs matthias.fuchs at esd-electronics.com
Fri Dec 28 11:56:14 CET 2007


This patch adds the first files for the new esd PMC440 boards.
The next two patches will complete the PMC440 board support.

Signed-off-by: Matthias Fuchs <matthias.fuchs at esd-electronics.com>
---
 board/{amcc/sequoia => esd/pmc440}/Makefile        |    4 +-
 board/{amcc/sequoia => esd/pmc440}/config.mk       |    0 
 board/{amcc/sequoia => esd/pmc440}/init.S          |   64 +--
 .../sequoia/sequoia.c => esd/pmc440/pmc440.c}      |  564 +++++++++++++++-----
 board/esd/pmc440/pmc440.h                          |  154 ++++++
 board/{amcc/sequoia => esd/pmc440}/sdram.c         |    0 
 board/{amcc/sequoia => esd/pmc440}/sdram.h         |    0 
 board/{amcc/sequoia => esd/pmc440}/u-boot-nand.lds |    0 
 board/{amcc/sequoia => esd/pmc440}/u-boot.lds      |    0 
 9 files changed, 595 insertions(+), 191 deletions(-)
 copy board/{amcc/sequoia => esd/pmc440}/Makefile (95%)
 copy board/{amcc/sequoia => esd/pmc440}/config.mk (100%)
 copy board/{amcc/sequoia => esd/pmc440}/init.S (71%)
 copy board/{amcc/sequoia/sequoia.c => esd/pmc440/pmc440.c} (57%)
 create mode 100644 board/esd/pmc440/pmc440.h
 copy board/{amcc/sequoia => esd/pmc440}/sdram.c (100%)
 copy board/{amcc/sequoia => esd/pmc440}/sdram.h (100%)
 copy board/{amcc/sequoia => esd/pmc440}/u-boot-nand.lds (100%)
 copy board/{amcc/sequoia => esd/pmc440}/u-boot.lds (100%)

diff --git a/board/amcc/sequoia/Makefile b/board/esd/pmc440/Makefile
similarity index 95%
copy from board/amcc/sequoia/Makefile
copy to board/esd/pmc440/Makefile
index e1c9ad4..4dd9c38 100644
--- a/board/amcc/sequoia/Makefile
+++ b/board/esd/pmc440/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_sequoia.o sdram.o
+COBJS	= $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
+	../common/cmd_loadpci.o
+
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/sequoia/config.mk b/board/esd/pmc440/config.mk
similarity index 100%
copy from board/amcc/sequoia/config.mk
copy to board/esd/pmc440/config.mk
diff --git a/board/amcc/sequoia/init.S b/board/esd/pmc440/init.S
similarity index 71%
copy from board/amcc/sequoia/init.S
copy to board/esd/pmc440/init.S
index c7da521..148af71 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/esd/pmc440/init.S
@@ -10,7 +10,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -20,57 +20,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-#define _256M       0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K	    0x00000000
-#define SZ_4K	    0x00000010
-#define SZ_16K	    0x00000020
-#define SZ_64K	    0x00000030
-#define SZ_256K	    0x00000040
-#define SZ_1M	    0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M	    0x00000070
-#define SZ_256M	    0x00000090
-
-/* Storage attributes */
-#define SA_W	    0x00000800	    /* Write-through */
-#define SA_I	    0x00000400	    /* Caching inhibited */
-#define SA_M	    0x00000200	    /* Memory coherence */
-#define SA_G	    0x00000100	    /* Guarded */
-#define SA_E	    0x00000080	    /* Endian */
-
-/* Access control */
-#define AC_X	    0x00000024	    /* Execute */
-#define AC_W	    0x00000012	    /* Write */
-#define AC_R	    0x00000009	    /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)		( (a)&0x00000fbf )
-
-#define tlbtab_start\
-	mflr    r1  ;\
-	bl 0f	    ;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;   \
-0:	mflr    r0	;   \
-	mtlr    r1	;   \
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -115,8 +67,13 @@ tlbtab:
 	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
 	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
 
-	/* TLB-entry for EBC */
-	tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	/* TLB-entries for EBC */
+	/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
+	 * tlb entry.
+	 * This dummy entry is only for convinience in order not to modify the
+	 * amount of entries. Currently OS/9 relies on this :-)
+	 */
+	tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB-entry for NAND */
 	tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
@@ -130,9 +87,10 @@ tlbtab:
 	/* TLB-entry for peripherals */
 	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
-	/* TLB-entry PCI IO Space - from sr at denx.de */
+	/* TLB-entry PCI IO space */
 	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+	/* TODO:  what about high IO space */
 	tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
diff --git a/board/amcc/sequoia/sequoia.c b/board/esd/pmc440/pmc440.c
similarity index 57%
copy from board/amcc/sequoia/sequoia.c
copy to board/esd/pmc440/pmc440.c
index f81f071..edf3a14 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/esd/pmc440/pmc440.c
@@ -1,5 +1,9 @@
 /*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com.
+ * Based on board/amcc/sequoia/sequoia.c
+ *
+ * (C) Copyright 2006
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
  * (C) Copyright 2006
@@ -28,12 +32,62 @@
 #include <ppc440.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <command.h>
+#include <i2c.h>
+#ifdef CONFIG_RESET_PHY_R
+#include <miiphy.h>
+#endif
+#include <serial.h>
+#include "fpga.h"
+#include "pmc440.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
-ulong flash_get_size (ulong base, int banknum);
+ulong flash_get_size(ulong base, int banknum);
+int pci_is_66mhz(void);
+int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+
+
+struct serial_device *default_serial_console(void)
+{
+	uchar buf[4];
+	ulong delay;
+	int i;
+	ulong val;
+
+	/*
+	 * Use default console on P4 when strapping jumper
+	 * is installed (bootstrap option != 'H').
+	 */
+	mfsdr(SDR_PINSTP, val);
+	if (((val & 0xf0000000) >> 29) != 7)
+		return &serial1_device;
+
+	ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
+	if (!(scratchreg & 0x80)) {
+		/* mark scratchreg valid */
+		scratchreg = (scratchreg & 0xffffff00) | 0x80;
+
+		i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
+		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
+			scratchreg |= buf[2];
+
+			/* bringup delay for console */
+			for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
+				udelay(1000);
+			}
+		} else
+			scratchreg |= 0x01;
+		out_be32((void*)GPIO0_ISR3L, scratchreg);
+	}
+
+	if (scratchreg & 0x01)
+		return &serial1_device;
+	else
+		return &serial0_device;
+}
 
 int board_early_init_f(void)
 {
@@ -41,90 +95,91 @@ int board_early_init_f(void)
 	u32 sdr0_pfc1, sdr0_pfc2;
 	u32 reg;
 
+	/* general EBC configuration (disable EBC timeouts) */
 	mtdcr(ebccfga, xbcfg);
-	mtdcr(ebccfgd, 0xb8400000);
+	mtdcr(ebccfgd, 0xf8400000);
 
 	/*--------------------------------------------------------------------
 	 * Setup the GPIO pins
+	 * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
 	 *-------------------------------------------------------------------*/
-	/* test-only: take GPIO init from pcs440ep ???? in config file */
-	out32(GPIO0_OR, 0x00000000);
-	out32(GPIO0_TCR, 0x0000000f);
-	out32(GPIO0_OSRL, 0x50015400);
-	out32(GPIO0_OSRH, 0x550050aa);
-	out32(GPIO0_TSRL, 0x50015400);
-	out32(GPIO0_TSRH, 0x55005000);
-	out32(GPIO0_ISR1L, 0x50000000);
+	out32(GPIO0_OR,    0x40000002);
+	out32(GPIO0_TCR,   0x4c90011f);
+	out32(GPIO0_OSRL,  0x28011400);
+	out32(GPIO0_OSRH,  0x55005000);
+	out32(GPIO0_TSRL,  0x08011400);
+	out32(GPIO0_TSRH,  0x55005000);
+	out32(GPIO0_ISR1L, 0x54000000);
 	out32(GPIO0_ISR1H, 0x00000000);
-	out32(GPIO0_ISR2L, 0x00000000);
+	out32(GPIO0_ISR2L, 0x44000000);
 	out32(GPIO0_ISR2H, 0x00000100);
 	out32(GPIO0_ISR3L, 0x00000000);
 	out32(GPIO0_ISR3H, 0x00000000);
 
-	out32(GPIO1_OR, 0x00000000);
-	out32(GPIO1_TCR, 0xc2000000);
-	out32(GPIO1_OSRL, 0x5c280000);
-	out32(GPIO1_OSRH, 0x00000000);
-	out32(GPIO1_TSRL, 0x0c000000);
-	out32(GPIO1_TSRH, 0x00000000);
-	out32(GPIO1_ISR1L, 0x00005550);
-	out32(GPIO1_ISR1H, 0x00000000);
-	out32(GPIO1_ISR2L, 0x00050000);
+	out32(GPIO1_OR,    0x80002408);
+	out32(GPIO1_TCR,   0xd6003c08);
+	out32(GPIO1_OSRL,  0x0a5a0000);
+	out32(GPIO1_OSRH,  0x00000000);
+	out32(GPIO1_TSRL,  0x00000000);
+	out32(GPIO1_TSRH,  0x00000000);
+	out32(GPIO1_ISR1L, 0x00005555);
+	out32(GPIO1_ISR1H, 0x40000000);
+	out32(GPIO1_ISR2L, 0x04010000);
 	out32(GPIO1_ISR2H, 0x00000000);
 	out32(GPIO1_ISR3L, 0x01400000);
 	out32(GPIO1_ISR3H, 0x00000000);
 
+	/* patch PLB:PCI divider for 66MHz PCI */
+	mfcpr(clk_spcid, reg);
+	if (pci_is_66mhz() && (reg != 0x02000000)) {
+		mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
+
+		mfcpr(clk_icfg, reg);
+		reg |= CPR0_ICFG_RLI_MASK;
+		mtcpr(clk_icfg, reg);
+
+		mtspr(dbcr0, 0x20000000); /* do chip reset */
+	}
+
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
 	mtdcr(uic0sr, 0xffffffff);	/* clear all */
 	mtdcr(uic0er, 0x00000000);	/* disable all */
 	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic0pr, 0xfffff7ef);
+	mtdcr(uic0tr, 0x00000000);
 	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(uic0sr, 0xffffffff);	/* clear all */
 
 	mtdcr(uic1sr, 0xffffffff);	/* clear all */
 	mtdcr(uic1er, 0x00000000);	/* disable all */
 	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic1pr, 0xffffc7f5);
+	mtdcr(uic1tr, 0x00000000);
 	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr(uic2sr, 0xffffffff);	/* clear all */
 	mtdcr(uic2er, 0x00000000);	/* disable all */
 	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic2pr, 0x27ffffff);
+	mtdcr(uic2tr, 0x00000000);
 	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(uic2sr, 0xffffffff);	/* clear all */
 
-	/* 50MHz tmrclk */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
-
-	/* clear write protects */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
-
-	/* enable Ethernet */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
-
-	/* enable USB device */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
-
 	/* select Ethernet pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
 	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
 	mfsdr(SDR0_PFC2, sdr0_pfc2);
 	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+
+	/* enable 2nd IIC */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
 	mtsdr(SDR0_PFC2, sdr0_pfc2);
 	mtsdr(SDR0_PFC1, sdr0_pfc1);
 
-	/* PCI arbiter enabled */
-	mfsdr(sdr_pci0, reg);
-	mtsdr(sdr_pci0, 0x80000000 | reg);
-
 	/* setup NAND FLASH */
 	mfsdr(SDR0_CUST0, sdr0_cust0);
 	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
@@ -145,12 +200,10 @@ int misc_init_r(void)
 	uint pbcr;
 	int size_val = 0;
 	u32 reg;
-#ifdef CONFIG_440EPX
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
 	char *act = getenv("usbact");
-#endif
 
 	/*
 	 * FLASH stuff...
@@ -163,7 +216,7 @@ int misc_init_r(void)
 	gd->bd->bi_flashoffset = 0;
 
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtdcr(ebccfga, pb3cr);
+	mtdcr(ebccfga, pb2cr);
 #else
 	mtdcr(ebccfga, pb0cr);
 #endif
@@ -196,7 +249,7 @@ int misc_init_r(void)
 	}
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtdcr(ebccfga, pb3cr);
+	mtdcr(ebccfga, pb2cr);
 #else
 	mtdcr(ebccfga, pb0cr);
 #endif
@@ -224,8 +277,8 @@ int misc_init_r(void)
 	/*
 	 * USB suff...
 	 */
-#ifdef CONFIG_440EPX
-	if (act == NULL || strcmp(act, "hostdev") == 0)	{
+	if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
 		/* SDR Setting */
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
 		mfsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -248,12 +301,8 @@ int misc_init_r(void)
 		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
 
-		/* To enable the USB 2.0 Device function through the UTMI interface */
 		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
-
 		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
 
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
 		mtsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -261,14 +310,14 @@ int misc_init_r(void)
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
 		/*clear resets*/
-		udelay (1000);
+		udelay(1000);
 		mtsdr(SDR0_SRST1, 0x00000000);
-		udelay (1000);
+		udelay(1000);
 		mtsdr(SDR0_SRST0, 0x00000000);
 
-		printf("USB:   Host(int phy) Device(ext phy)\n");
+		printf("USB:   Host\n");
 
-	} else if (strcmp(act, "dev") == 0) {
+	} else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 		/*-------------------PATCH-------------------------------*/
 		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
@@ -318,7 +367,6 @@ int misc_init_r(void)
 		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
 
 		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
 
 		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
@@ -329,18 +377,13 @@ int misc_init_r(void)
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
 
 		/*clear resets*/
-		udelay (1000);
+		udelay(1000);
 		mtsdr(SDR0_SRST1, 0x00000000);
-		udelay (1000);
+		udelay(1000);
 		mtsdr(SDR0_SRST0, 0x00000000);
 
-		printf("USB:   Device(int phy)\n");
+		printf("USB:   Device\n");
 	}
-#endif /* CONFIG_440EPX */
-
-	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
-	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
-	mtsdr(SDR0_SRST1, reg);
 
 	/*
 	 * Clear PLB4A0_ACR[WRP]
@@ -350,69 +393,63 @@ int misc_init_r(void)
 	reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
 	mtdcr(plb4_acr, reg);
 
+#ifdef CONFIG_FPGA
+	pmc440_init_fpga();
+#endif
+
+	/* turn off POST LED */
+	out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
+	/* turn on RUN LED */
+	out_be32((void*)GPIO0_OR,  in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
 	return 0;
 }
 
-int checkboard(void)
+int is_monarch(void)
 {
-	char *s = getenv("serial#");
-	u8 rev;
-	u8 val;
-
-#ifdef CONFIG_440EPX
-	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
-#else
-	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
-#endif
+	if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
+		return 0;
 
-	rev = in_8((void *)(CFG_BCSR_BASE + 0));
-	val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
-	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+	return 1;
+}
 
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-	putc('\n');
+int pci_is_66mhz(void)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
+		return 1;
+	return 0;
+}
 
-	return (0);
+int board_revision(void)
+{
+	return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
+int checkboard(void)
 {
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
+	puts("Board: esd GmbH - PMC440");
 
-	mtmsr(0);
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld, ", gd->board_type);
 
-	for (k = 0; k < CFG_MBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
+	if (!is_monarch()) {
+		puts("non-");
+	}
 
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
+	printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
+	return (0);
+}
 
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices. Some OSs rely on this.
+ */
+void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+				   int_line[PCI_DEV(dev) & 0x03]);
 }
 #endif
 
@@ -467,6 +504,10 @@ int pci_pre_init(struct pci_controller *hose)
 	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 	mtdcr(plb1_acr, addr);
 
+#ifdef CONFIG_PCI_PNP
+	hose->fixup_irq = pmc440_pci_fixup_irq;
+#endif
+
 	return 1;
 }
 #endif /* defined(CONFIG_PCI) */
@@ -488,7 +529,7 @@ void pci_target_init(struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	  | PowerPC440EPX PCI Master configuration.
 	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
@@ -496,30 +537,39 @@ void pci_target_init(struct pci_controller *hose)
 	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
 	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+	out32r(PCIX0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, and enable region */
+
+	if (!is_monarch()) {
+		/* BAR1: top 64MB of RAM */
+		out32r(PCIX0_PTM1MS, 0xfc000001);	/* Memory Size/Attribute */
+		out32r(PCIX0_PTM1LA, 0x0c000000);       /* Local Addr. Reg */
+	} else {
+		/* BAR1: complete 256MB RAM (TODO: make dynamic) */
+		out32r(PCIX0_PTM1MS, 0xf0000001);	/* Memory Size/Attribute */
+		out32r(PCIX0_PTM1LA, 0x00000000);       /* Local Addr. Reg */
+	}
 
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+	/* BAR2: 16 MB FPGA registers */
+	out32r(PCIX0_PTM2MS, 0xff000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0xef000000);	/* Local Addr. Reg */
 
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+	if (is_monarch()) {
+		/* BAR2: map FPGA registers behind system memory at 1GB */
+		pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
+	}
 
 	/*--------------------------------------------------------------------------+
 	 * Set up Configuration registers
 	 *--------------------------------------------------------------------------*/
 
-	/* Program the board's subsystem id/vendor id */
+	/* Program the board's vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 
+#if 0   /* disabled for PMC405 backward compatibility */
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+#endif
 
 	/* 240nS PCI clock */
 	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
@@ -529,8 +579,25 @@ void pci_target_init(struct pci_controller *hose)
 
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
+	if (!is_monarch()) {
+		/* Program the board's subsystem id/classcode */
+		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
+				      CFG_PCI_SUBSYS_ID_NONMONARCH);
+		pci_write_config_word(0, PCI_CLASS_SUB_CODE,
+				      CFG_PCI_CLASSCODE_NONMONARCH);
+
+		/* PCI configuration done: release ERREADY */
+		out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR)  | GPIO1_PPC_EREADY);
+		out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
+	} else {
+		/* Program the board's subsystem id/classcode */
+		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
+				      CFG_PCI_SUBSYS_ID_MONARCH);
+		pci_write_config_word(0, PCI_CLASS_SUB_CODE,
+				      CFG_PCI_CLASSCODE_MONARCH);
+	}
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
@@ -546,12 +613,42 @@ void pci_master_init(struct pci_controller *hose)
 	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 	  +--------------------------------------------------------------------------*/
-	pci_read_config_word(0, PCI_COMMAND, &temp_short);
-	pci_write_config_word(0, PCI_COMMAND,
-			      temp_short | PCI_COMMAND_MASTER |
-			      PCI_COMMAND_MEMORY);
+	if (is_monarch()) {
+		pci_read_config_word(0, PCI_COMMAND, &temp_short);
+		pci_write_config_word(0, PCI_COMMAND,
+				      temp_short | PCI_COMMAND_MASTER |
+				      PCI_COMMAND_MEMORY);
+	}
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+
+static void wait_for_pci_ready(void)
+{
+	int i;
+	char *s = getenv("pcidelay");
+	if (s) {
+		int ms = simple_strtoul(s, NULL, 10);
+		printf("PCI:   Waiting for %d ms\n", ms);
+		for (i=0; i<ms; i++)
+			udelay(1000);
+	}
+
+	if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
+		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
+		while (1) {
+			if (ctrlc()) {
+				puts("abort\n");
+				break;
+			}
+			if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
+				printf("done\n");
+				break;
+			}
+		}
+	}
+}
+
 
 /*************************************************************************
  *  is_pci_host
@@ -571,10 +668,19 @@ void pci_master_init(struct pci_controller *hose)
 #if defined(CONFIG_PCI)
 int is_pci_host(struct pci_controller *hose)
 {
-	/* Cactus is always configured as host. */
-	return (1);
+	char *s = getenv("pciscan");
+	if (s == NULL)
+		if (is_monarch()) {
+			wait_for_pci_ready();
+			return 1;
+		} else
+			return 0;
+	else if (!strcmp(s, "yes"))
+		return 1;
+
+	return 0;
 }
-#endif				/* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) */
 #if defined(CONFIG_POST)
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests
@@ -586,6 +692,190 @@ int post_hotkeys_pressed(void)
 }
 #endif /* CONFIG_POST */
 
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+	if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
+	}
+
+	if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
+	}
+}
+#endif
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP));
+			break;
+		}
+	}
+	return state;
+}
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+
+#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+#if defined(CFG_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 1);
+#endif
+	/* Write data until done or would cross a write page boundary.
+	 * We must write the address again when changing pages
+	 * because the address counter only increments within a page.
+	 */
+
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen	= 2;
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+#define	BOOT_EEPROM_PAGE_SIZE	   (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define	BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+		maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+			rcode = 1;
+
+		buffer += len;
+		offset += len;
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+	}
+#if defined(CFG_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 0);
+#endif
+	return rcode;
+}
+
+
+int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+	/* Read data until done or would cross a page boundary.
+	 * We must write the address again when changing pages
+	 * because the next page may be in a different device.
+	 */
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen	= 2;
+
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+		maxlen = 0x100 - blk_off;
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+			rcode = 1;
+		buffer += len;
+		offset += len;
+	}
+
+	return rcode;
+}
+
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+	char *act = getenv("usbact");
+	int i;
+
+	if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
+		/* enable power on USB socket */
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+
+	for (i=0; i<1000; i++)
+		udelay(1000);
+
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	/* disable power on USB socket */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
+	return 0;
+}
+
+int usb_board_init_fail(void)
+{
+	usb_board_stop();
+	return 0;
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
new file mode 100644
index 0000000..7e70fd1
--- /dev/null
+++ b/board/esd/pmc440/pmc440.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PMC440_H__
+#define __PMC440_H__
+
+
+/*-----------------------------------------------------------------------
+ * GPIOs
+ */
+#define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
+#define GPIO1_NONMONARCH          (0x80000000 >> (63-32)) /* GPIO63 I */
+#define GPIO1_PPC_EREADY          (0x80000000 >> (62-32)) /* GPIO62 I/O */
+#define GPIO1_M66EN               (0x80000000 >> (61-32)) /* GPIO61 I */
+#define GPIO1_POST_N              (0x80000000 >> (60-32)) /* GPIO60 O */
+#define GPIO1_IOEN_N              (0x80000000 >> (50-32)) /* GPIO50 O */
+#define GPIO1_HWID_MASK           (0xf0000000 >> (56-32)) /* GPIO56..59 I */
+
+#define GPIO1_USB_PWR_N           (0x80000000 >> (32-32)) /* GPIO32 I */
+#define GPIO0_LED_RUN_N           (0x80000000 >> 30)      /* GPIO30 O */
+#define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
+#define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
+#define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
+#define GPIO0_SELF_RST            (0x80000000 >> 6)       /* GPIO6  OD */
+
+/* FPGA programming pin configuration */
+#define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
+#define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
+#define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
+#define GPIO1_FPGA_DONE           (0x80000000 >> (55-32)) /* FPGA done pin (ppc input)     */
+#define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
+#define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
+
+/*-----------------------------------------------------------------------
+ * FPGA interface
+ */
+#define FPGA_BA CFG_FPGA_BASE0
+#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
+#define FPGA_IN32(p) in_be32((void*)(p))
+#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
+#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
+
+struct pmc440_fifo_s {
+	u32 data;
+	u32 ctrl;
+};
+
+/* fifo ctrl register */
+#define FIFO_IE              (1 << 15)
+#define FIFO_OVERFLOW        (1 << 10)
+#define FIFO_EMPTY           (1 <<  9)
+#define FIFO_FULL            (1 <<  8)
+#define FIFO_LEVEL_MASK      0x000000ff
+
+#define FIFO_COUNT           4
+
+struct pmc440_fpga_s {
+	u32 ctrla;
+	u32 status;
+	u32 ctrlb;
+	u32 pad1[0x40 / sizeof(u32) - 3];
+	u32 irig_time;                  /* offset: 0x0040 */
+	u32 irig_tod;
+	u32 irig_cf;
+	u32 pad2;
+	u32 irig_rx_time;               /* offset: 0x0050 */
+	u32 pad3[3];
+	u32 hostctrl;                   /* offset: 0x0060 */
+	u32 pad4[0x20 / sizeof(u32) - 1];
+	struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
+};
+
+typedef struct pmc440_fpga_s pmc440_fpga_t;
+
+/* ctrl register */
+#define CTRL_HOST_IE         (1 <<  8)
+
+/* outputs */
+#define RESET_EN    (1 << 31)
+#define CLOCK_EN    (1 << 30)
+#define RESET_OUT   (1 << 19)
+#define CLOCK_OUT   (1 << 22)
+#define RESET_OUT   (1 << 19)
+#define IRIGB_R_OUT (1 << 14)
+
+
+/* status register */
+#define STATUS_VERSION_SHIFT 24
+#define STATUS_VERSION_MASK  0xff000000
+#define STATUS_HWREV_SHIFT   20
+#define STATUS_HWREV_MASK    0x00f00000
+
+#define STATUS_CAN_ISF       (1 << 11)
+#define STATUS_CSTM_ISF      (1 << 10)
+#define STATUS_FIFO_ISF      (1 <<  9)
+#define STATUS_HOST_ISF      (1 <<  8)
+
+
+/* inputs */
+#define RESET_IN    (1 << 0)
+#define CLOCK_IN    (1 << 1)
+#define IRIGB_R_IN  (1 << 5)
+
+
+/* hostctrl register */
+#define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
+#define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
+#define HOSTCTRL_CSTM1IE_GATE (1 <<  7)
+#define HOSTCTRL_CSTM1IW_FLAG (1 <<  6)
+#define HOSTCTRL_CSTM0IE_GATE (1 <<  5)
+#define HOSTCTRL_CSTM0IW_FLAG (1 <<  4)
+#define HOSTCTRL_FIFOIE_GATE (1 <<  3)
+#define HOSTCTRL_FIFOIE_FLAG (1 <<  2)
+#define HOSTCTRL_HCINT_GATE  (1 <<  1)
+#define HOSTCTRL_HCINT_FLAG  (1 <<  0)
+
+#define NGCC_CTRL_BASE         (CFG_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_FPGARST_N    (1 <<  2)
+
+/*-----------------------------------------------------------------------
+ * FPGA to PPC interrupt
+ */
+#define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */
+#define IRQ1_FPGA            (32+30) /* UIC1 - custom module */
+#define IRQ2_FPGA            (64+ 3) /* UIC2 - custom module / CAN */
+#define IRQ_ETH0             (64+ 4) /* UIC2 */
+#define IRQ_ETH1             (   27) /* UIC0 */
+#define IRQ_RTC              (64+ 0) /* UIC2 */
+#define IRQ_PCIA             (64+ 1) /* UIC2 */
+#define IRQ_PCIB             (32+18) /* UIC1 */
+#define IRQ_PCIC             (32+19) /* UIC1 */
+#define IRQ_PCID             (32+20) /* UIC1 */
+
+#endif /* __PMC440_H__ */
diff --git a/board/amcc/sequoia/sdram.c b/board/esd/pmc440/sdram.c
similarity index 100%
copy from board/amcc/sequoia/sdram.c
copy to board/esd/pmc440/sdram.c
diff --git a/board/amcc/sequoia/sdram.h b/board/esd/pmc440/sdram.h
similarity index 100%
copy from board/amcc/sequoia/sdram.h
copy to board/esd/pmc440/sdram.h
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds
similarity index 100%
copy from board/amcc/sequoia/u-boot-nand.lds
copy to board/esd/pmc440/u-boot-nand.lds
diff --git a/board/amcc/sequoia/u-boot.lds b/board/esd/pmc440/u-boot.lds
similarity index 100%
copy from board/amcc/sequoia/u-boot.lds
copy to board/esd/pmc440/u-boot.lds
-- 
1.5.3





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