[U-Boot-Users] [PATCH 2/2] mpc85xx: Add support for ATUM8548 (updated)
Andy Fleming
afleming at gmail.com
Wed Jan 9 08:57:32 CET 2008
Applied both, thanks!
I modified the init.S file to conform to Kumar's changes to the TLB
macros, just so you know. Please take a look to make sure I didn't
break anything (I just did a compile test)
On 12/21/07, robert lazarski <robertlazarski at gmail.com> wrote:
> Add support for Instituto Atlantico's ATUM8548 board
>
> Signed-off-by: robert lazarski <robertlazarski at gmail.com>
>
> diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile
> new file mode 100644
> index 0000000..e198062
> --- /dev/null
> +++ b/board/atum8548/Makefile
> @@ -0,0 +1,56 @@
> +#
> +# Copyright 2004 Freescale Semiconductor.
> +# (C) Copyright 2001-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +ifneq ($(OBJTREE),$(SRCTREE))
> +$(shell mkdir -p $(obj)../common)
> +endif
> +
> +LIB = $(obj)lib$(BOARD).a
> +
> +COBJS := $(BOARD).o
> +
> +SOBJS := init.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +clean:
> + rm -f $(OBJS) $(SOBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak .depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
> new file mode 100644
> index 0000000..4d7dc77
> --- /dev/null
> +++ b/board/atum8548/atum8548.c
> @@ -0,0 +1,420 @@
> +/*
> + * Copyright 2007
> + * Robert Lazarski, Instituto Atlantico, robertlazarski at gmail.com
> + *
> + * Copyright 2007 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <pci.h>
> +#include <asm/processor.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/immap_fsl_pci.h>
> +#include <asm/io.h>
> +#include <spd.h>
> +#include <miiphy.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +
> +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> +extern void ddr_enable_ecc(unsigned int dram_size);
> +#endif
> +
> +extern long int spd_sdram(void);
> +long int fixed_sdram(void);
> +
> +int board_early_init_f (void)
> +{
> + return 0;
> +}
> +
> +int checkboard (void)
> +{
> + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
> + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
> + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
> +
> + if ((uint)&gur->porpllsr != 0xe00e0000) {
> + printf("immap size error %x\n",&gur->porpllsr);
> + }
> + printf ("Board: ATUM8548\n");
> +
> + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
> + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
> + ecm->eedr = 0xffffffff; /* Clear ecm errors */
> + ecm->eeer = 0xffffffff; /* Enable ecm errors */
> +
> + return 0;
> +}
> +
> +#if !defined(CONFIG_SPD_EEPROM)
> +/*************************************************************************
> + * fixed sdram init -- doesn't use serial presence detect.
> + ************************************************************************/
> +long int fixed_sdram (void)
> +{
> + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
> +
> + ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
> + ddr->cs0_config = CFG_DDR_CS0_CONFIG;
> + ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
> + ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
> + ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
> + ddr->sdram_mode = CFG_DDR_MODE;
> + ddr->sdram_interval = CFG_DDR_INTERVAL;
> + #if defined (CONFIG_DDR_ECC)
> + ddr->err_disable = 0x0000000D;
> + ddr->err_sbe = 0x00ff0000;
> + #endif
> + asm("sync;isync;msync");
> + udelay(500);
> + #if defined (CONFIG_DDR_ECC)
> + /* Enable ECC checking */
> + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
> + #else
> + ddr->sdram_cfg = CFG_DDR_CONTROL;
> + #endif
> + asm("sync; isync; msync");
> + udelay(500);
> + return CFG_SDRAM_SIZE * 1024 * 1024;
> +}
> +#endif /* !defined(CONFIG_SPD_EEPROM) */
> +
> +long int
> +initdram(int board_type)
> +{
> + long dram_size = 0;
> +
> + puts("Initializing\n");
> +
> +#if defined(CONFIG_SPD_EEPROM)
> + puts("spd_sdram\n");
> + dram_size = spd_sdram ();
> +#else
> + puts("fixed_sdram\n");
> + dram_size = fixed_sdram ();
> +#endif
> +
> +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> + /*
> + * Initialize and enable DDR ECC.
> + */
> + ddr_enable_ecc(dram_size);
> +#endif
> + puts(" DDR: ");
> + return dram_size;
> +}
> +
> +#if defined(CFG_DRAM_TEST)
> +int
> +testdram(void)
> +{
> + uint *pstart = (uint *) CFG_MEMTEST_START;
> + uint *pend = (uint *) CFG_MEMTEST_END;
> + uint *p;
> +
> + printf("Testing DRAM from 0x%08x to 0x%08x\n",
> + CFG_MEMTEST_START,
> + CFG_MEMTEST_END);
> +
> + printf("DRAM test phase 1:\n");
> + for (p = pstart; p < pend; p++) {
> + printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
> + *p = 0xaaaaaaaa;
> + }
> +
> + for (p = pstart; p < pend; p++) {
> + if (*p != 0xaaaaaaaa) {
> + printf ("DRAM test fails at: %08x\n", (uint) p);
> + return 1;
> + }
> + }
> +
> + printf("DRAM test phase 2:\n");
> + for (p = pstart; p < pend; p++)
> + *p = 0x55555555;
> +
> + for (p = pstart; p < pend; p++) {
> + if (*p != 0x55555555) {
> + printf ("DRAM test fails at: %08x\n", (uint) p);
> + return 1;
> + }
> + }
> +
> + printf("DRAM test passed.\n");
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_PCI1
> +static struct pci_controller pci1_hose;
> +#endif
> +
> +#ifdef CONFIG_PCI2
> +static struct pci_controller pci2_hose;
> +#endif
> +
> +#ifdef CONFIG_PCIE1
> +static struct pci_controller pcie1_hose;
> +#endif
> +
> +int first_free_busno=0;
> +
> +void
> +pci_init_board(void)
> +{
> + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
> +
> + uint devdisr = gur->devdisr;
> + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
> + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
> +
> + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
> + devdisr, io_sel, host_agent);
> +
> + /* explicitly set 'Clock out select register' to echo SYSCLK
> input to our CPLD */
> + gur->clkocr |= MPC85xx_ATUM_CLKOCR;
> +
> + if (io_sel & 1) {
> + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
> + printf (" eTSEC1 is in sgmii mode.\n");
> + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
> + printf (" eTSEC2 is in sgmii mode.\n");
> + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
> + printf (" eTSEC3 is in sgmii mode.\n");
> + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
> + printf (" eTSEC4 is in sgmii mode.\n");
> + }
> +
> +#ifdef CONFIG_PCIE1
> + {
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
> + extern void fsl_pci_init(struct pci_controller *hose);
> + struct pci_controller *hose = &pcie1_hose;
> + int pcie_ep = (host_agent == 5);
> + int pcie_configured = io_sel & 6;
> +
> + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
> + printf ("\n PCIE1 connected to slot as %s (base address %x)",
> + pcie_ep ? "End Point" : "Root Complex",
> + (uint)pci);
> + if (pci->pme_msg_det) {
> + pci->pme_msg_det = 0xffffffff;
> + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
> + }
> + printf ("\n");
> +
> + /* inbound */
> + pci_set_region(hose->regions + 0,
> + CFG_PCI_MEMORY_BUS,
> + CFG_PCI_MEMORY_PHYS,
> + CFG_PCI_MEMORY_SIZE,
> + PCI_REGION_MEM | PCI_REGION_MEMORY);
> +
> + /* outbound memory */
> + pci_set_region(hose->regions + 1,
> + CFG_PCIE1_MEM_BASE,
> + CFG_PCIE1_MEM_PHYS,
> + CFG_PCIE1_MEM_SIZE,
> + PCI_REGION_MEM);
> +
> + /* outbound io */
> + pci_set_region(hose->regions + 2,
> + CFG_PCIE1_IO_BASE,
> + CFG_PCIE1_IO_PHYS,
> + CFG_PCIE1_IO_SIZE,
> + PCI_REGION_IO);
> +
> + hose->region_count = 3;
> +#ifdef CFG_PCIE1_MEM_BASE2
> + /* outbound memory */
> + pci_set_region(hose->regions + 3,
> + CFG_PCIE1_MEM_BASE2,
> + CFG_PCIE1_MEM_PHYS2,
> + CFG_PCIE1_MEM_SIZE2,
> + PCI_REGION_MEM);
> + hose->region_count++;
> +#endif
> + hose->first_busno=first_free_busno;
> +
> + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
> +
> + fsl_pci_init(hose);
> +
> + first_free_busno=hose->last_busno+1;
> + printf(" PCIE1 on bus %02x - %02x\n",
> + hose->first_busno,hose->last_busno);
> +
> + } else {
> + printf (" PCIE1: disabled\n");
> + }
> +
> + }
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
> +#endif
> +
> +#ifdef CONFIG_PCI1
> +{
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
> + extern void fsl_pci_init(struct pci_controller *hose);
> + struct pci_controller *hose = &pci1_hose;
> +
> + uint pci_agent = (host_agent == 6);
> + uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
> + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
> + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
> + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /*
> PORPLLSR[16] */
> +
> + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
> + printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
> + (pci_32) ? 32 : 64,
> + (pci_speed == 33333000) ? "33" :
> + (pci_speed == 66666000) ? "66" : "unknown",
> + pci_clk_sel ? "sync" : "async",
> + pci_agent ? "agent" : "host",
> + pci_arb ? "arbiter" : "external-arbiter",
> + (uint)pci
> + );
> +
> + /* inbound */
> + pci_set_region(hose->regions + 0,
> + CFG_PCI_MEMORY_BUS,
> + CFG_PCI_MEMORY_PHYS,
> + CFG_PCI_MEMORY_SIZE,
> + PCI_REGION_MEM | PCI_REGION_MEMORY);
> +
> + /* outbound memory */
> + pci_set_region(hose->regions + 1,
> + CFG_PCI1_MEM_BASE,
> + CFG_PCI1_MEM_PHYS,
> + CFG_PCI1_MEM_SIZE,
> + PCI_REGION_MEM);
> +
> + /* outbound io */
> + pci_set_region(hose->regions + 2,
> + CFG_PCI1_IO_BASE,
> + CFG_PCI1_IO_PHYS,
> + CFG_PCI1_IO_SIZE,
> + PCI_REGION_IO);
> + hose->region_count = 3;
> + hose->first_busno=first_free_busno;
> + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
> +
> + fsl_pci_init(hose);
> + first_free_busno=hose->last_busno+1;
> + printf ("PCI1 on bus %02x - %02x\n",
> + hose->first_busno,hose->last_busno);
> + } else {
> + printf (" PCI1: disabled\n");
> + }
> +}
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
> +#endif
> +
> +#ifdef CONFIG_PCI2
> +{
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
> + extern void fsl_pci_init(struct pci_controller *hose);
> + struct pci_controller *hose = &pci2_hose;
> +
> + if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
> + pci_set_region(hose->regions + 0,
> + CFG_PCI_MEMORY_BUS,
> + CFG_PCI_MEMORY_PHYS,
> + CFG_PCI_MEMORY_SIZE,
> + PCI_REGION_MEM | PCI_REGION_MEMORY);
> +
> + pci_set_region(hose->regions + 1,
> + CFG_PCI2_MEM_BASE,
> + CFG_PCI2_MEM_PHYS,
> + CFG_PCI2_MEM_SIZE,
> + PCI_REGION_MEM);
> +
> + pci_set_region(hose->regions + 2,
> + CFG_PCI2_IO_BASE,
> + CFG_PCI2_IO_PHYS,
> + CFG_PCI2_IO_SIZE,
> + PCI_REGION_IO);
> + hose->region_count = 3;
> + hose->first_busno=first_free_busno;
> + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
> +
> + fsl_pci_init(hose);
> + first_free_busno=hose->last_busno+1;
> + printf ("PCI2 on bus %02x - %02x\n",
> + hose->first_busno,hose->last_busno);
> + } else {
> + printf (" PCI2: disabled\n");
> + }
> +}
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCI2;
> +#endif
> +}
> +
> +
> +int last_stage_init(void)
> +{
> + int ic = icache_status ();
> + printf ("icache_status: %d\n", ic);
> + return 0;
> +}
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +
> +void
> +ft_board_setup(void *blob, bd_t *bd)
> +{
> + int node, tmp[2];
> + const char *path;
> +
> + ft_cpu_setup(blob, bd);
> +
> + node = fdt_path_offset(blob, "/aliases");
> + tmp[0] = 0;
> + if (node >= 0) {
> +#ifdef CONFIG_PCI1
> + path = fdt_getprop(blob, node, "pci0", NULL);
> + if (path) {
> + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
> + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
> + }
> +#endif
> +#ifdef CONFIG_PCI2
> + path = fdt_getprop(blob, node, "pci1", NULL);
> + if (path) {
> + tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
> + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
> + }
> +#endif
> +#ifdef CONFIG_PCIE1
> + path = fdt_getprop(blob, node, "pci2", NULL);
> + if (path) {
> + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
> + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
> + }
> +#endif
> + }
> +}
> +#endif
> diff --git a/board/atum8548/config.mk b/board/atum8548/config.mk
> new file mode 100644
> index 0000000..9065817
> --- /dev/null
> +++ b/board/atum8548/config.mk
> @@ -0,0 +1,33 @@
> +#
> +# Copyright 2004, 2007 Freescale Semiconductor.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +#
> +# atum8548 board
> +# TEXT_BASE = 0xfff80000
> +# TEXT_BASE = 0xfffff000
> +ifndef TEXT_BASE
> +TEXT_BASE = 0xfff80000
> +endif
> +
> +PLATFORM_CPPFLAGS += -DCONFIG_E500=1
> +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
> +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
> diff --git a/board/atum8548/init.S b/board/atum8548/init.S
> new file mode 100644
> index 0000000..2f016ab
> --- /dev/null
> +++ b/board/atum8548/init.S
> @@ -0,0 +1,242 @@
> +/*
> + * Copyright 2007
> + * Robert Lazarski, Instituto Atlantico, robertlazarski at gmail.com
> + * Copyright 2004, 2007 Freescale Semiconductor.
> + * Copyright 2002,2003, Motorola Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <ppc_asm.tmpl>
> +#include <ppc_defs.h>
> +#include <asm/cache.h>
> +#include <asm/mmu.h>
> +#include <config.h>
> +#include <mpc85xx.h>
> +
> +#define LAWAR_TRGT_PCI1 0x00000000
> +#define LAWAR_TRGT_PCI2 0x00100000
> +#define LAWAR_TRGT_PCIE 0x00200000
> +#define LAWAR_TRGT_DDR 0x00f00000
> +
> +/*
> + * TLB0 and TLB1 Entries
> + *
> + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
> + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
> + * these TLB entries are established.
> + *
> + * The TLB entries for DDR are dynamically setup in spd_sdram()
> + * and use TLB1 Entries 8 through 15 as needed according to the
> + * size of DDR memory.
> + *
> + * MAS0: tlbsel, esel, nv
> + * MAS1: valid, iprot, tid, ts, tsize
> + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
> + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
> + */
> +
> +#define entry_start \
> + mflr r1 ; \
> + bl 0f ;
> +
> +#define entry_end \
> +0: mflr r0 ; \
> + mtlr r1 ; \
> + blr ;
> +
> +
> + .section .bootpg, "ax"
> + .globl tlb1_entry
> +tlb1_entry:
> + entry_start
> +
> + /*
> + * Number of TLB0 and TLB1 entries in the following table
> + */
> + .long (2f-1f)/16
> +
> +1:
> +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
> + /*
> + * TLB0 4K Non-cacheable, guarded
> + * 0xff700000 4K Initial CCSRBAR mapping
> + *
> + * This ends up at a TLB0 Index==0 entry, and must not collide
> + * with other TLB0 Entries.
> + */
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
> +#else
> +#error("Update the number of table entries in tlb1_entry")
> +#endif
> +
> + /*
> + * TLB0 16K Cacheable, guarded
> + * Temporary Global data for initialization
> + *
> + * Use four 4K TLB0 entries. These entries must be cacheable
> + * as they provide the bootstrap memory before the memory
> + * controler and real memory have been configured.
> + *
> + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
> + * and must not collide with other TLB0 entries.
> + */
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
> + 0,0,0,0,0,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
> + 0,0,0,0,0,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
> + 0,0,0,0,0,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
> + 0,0,0,0,0,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + /* TLB 1 Initializations */
> + /*
> + * TLB 0, 1: 128M Non-cacheable, guarded
> + * 0xf8000000 128M FLASH
> + * Out of reset this entry is only 4K.
> + */
> + .long TLB1_MAS0(1, 0, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x4000000),
> + 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x4000000),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(1, 1, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 2: 1G Non-cacheable, guarded
> + * 0x80000000 1G PCI1/PCIE 8,9,a,b
> + */
> + .long TLB1_MAS0(1, 2, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 3, 4: 512M Non-cacheable, guarded
> + * 0xc0000000 1G PCI2
> + */
> + .long TLB1_MAS0(1, 3, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_PHYS),
> + 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
> + .long TLB1_MAS0(1, 4, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_PHYS + 0x10000000),
> + 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_PHYS + 0x10000000),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 5: 64M Non-cacheable, guarded
> + * 0xe000_0000 1M CCSRBAR
> + * 0xe200_0000 1M PCI1 IO
> + * 0xe210_0000 1M PCI2 IO
> + * 0xe300_0000 1M PCIe IO
> + */
> + .long TLB1_MAS0(1, 5, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
> +
> +2:
> + entry_end
> +
> +/*
> + * LAW(Local Access Window) configuration:
> + *
> + * 0x0000_0000 0x7fff_ffff DDR 2G
> + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
> + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
> + * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
> + * 0xe000_0000 0xe000_ffff CCSR 1M
> + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
> + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
> + * 0xe300_0000 0xe30f_ffff PCIe IO 1M
> + * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
> + *
> + * Notes:
> + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
> + * If flash is 8M at default position (last 8M), no LAW needed.
> + *
> + * LAW 0 is reserved for boot mapping
> + */
> +
> + .section .bootpg, "ax"
> + .globl law_entry
> +law_entry:
> + entry_start
> +
> + .long (4f-3f)/8
> +3:
> + .long 0
> + .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN
> +
> + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
> +
> + .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
> +
> + .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
> +
> + .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
> +
> + .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
> +
> + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
> +
> + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
> + .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
> + .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
> +
> +4:
> + entry_end
>
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