[U-Boot-Users] [PATCH 1/1] Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock

[Kim Phillips]

On Mon, 24 Mar 2008 13:00:59 -0400
"Joe D'Abbraccio" <Joe.D'abbraccio at freescale.com> wrote:

> From: Joe D'Abbraccio <ljd015 at freescale.com>
> 
> With the original value of 1/2 clock cycle delay, the system ran relatively
> stable except when we run benchmarks that are intensive users of memory.
> When I run samba connected disk with a HDBENCH test, the system locks-up
> or reboots sporadically.
> 
> Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio at freescale.com>
> ---
>  include/configs/MPC8349ITX.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)

applied.

Thanks,

Kim