[U-Boot-Users] RE: [PATCH] ARM: Davinci: Fix DM644x timer overflow handling and cleanup
Pieter Voorthuijsen
pieter.voorthuijsen at Prodrive.nl
Tue Mar 25 11:06:31 CET 2008
Hi Dirk, Troy,
Still some troubles on the DVEVM, i2c and flash are too fast, also dhcp is racing like h#ll. See log below.
Currently the timer rolls over every 1 ms, this means get_timer should be called at least every ms to detect a roll over... Is it better to have a static variable timer than read the timer register directly?
I see that this is standard behavior in other timer code in u-boot, but we don't need it I think. I'll try to implement the 64-bit timer without roll over this afternoon.
Best regards, Pieter
U-Boot > era 03EC0000 +20000
Flash erase timeout at address 3ec0000 data b4f0b4f
Flash erase timeout at address 3ed0000 data f4f0f4f
done
Erased 2 sectors
U-Boot > iprobe
Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0B 0C 0D 0E 0F 10 11 12 13 1
4 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E
2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49
4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 6
4 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E
7F
U-Boot >
-----Original Message-----
From: dirk.behme at googlemail.com [mailto:dirk.behme at googlemail.com]
Sent: maandag 24 maart 2008 15:58
To: u-boot-users at lists.sourceforge.net
Cc: troy.kisky at boundarydevices.com; Pieter Voorthuijsen
Subject: [PATCH] ARM: Davinci: Fix DM644x timer overflow handling and cleanup
Fix ARM based DaVinci DM644x timer overflow handling and cleanup timer code.
Changes:
- Remove *_masked() functions as noted by Wolfgang
- Adapt register naming to recent TI spec (sprue26, March 2007)
- Fix reset_timer() handling
- As reported by Pieter [1] the overflow fix introduced a delay of factor 16 (e.g 2 seconds became 32). While the overflow fix is basically okay, it missed to divide CFG_HZ_CLOCK by 16, too. Fix this.
[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/38179
- Remove software division of timer count value (DIV(x) macro) and do it in hardware (TIM_CLK_DIV).
Many thanks to Troy Kisky <troy.kisky at boundarydevices.com> for his hints!
Patch is compile tested with davinci_dvevm & sonata & schmoogie configuration. Anybody can test it on real hardware? Pieter?
Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
Index: uboot_davinci/cpu/arm926ejs/davinci/timer.c
===================================================================
--- uboot_davinci.orig/cpu/arm926ejs/davinci/timer.c
+++ uboot_davinci/cpu/arm926ejs/davinci/timer.c
@@ -42,9 +42,9 @@
typedef volatile struct {
u_int32_t pid12;
- u_int32_t emumgt_clksped;
- u_int32_t gpint_en;
- u_int32_t gpdir_dat;
+ u_int32_t emumgt;
+ u_int32_t na1;
+ u_int32_t na2;
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
@@ -52,21 +52,11 @@ typedef volatile struct {
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
- u_int32_t tlgc;
- u_int32_t tlmr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
-#define READ_TIMER timer->tim34
-
-/*
- * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
- * around of timestamp already after min ~159s, divide it, e.g. by 16.
- * timestamp will then wrap around all min ~42min
- */
-#define DIV(x) ((x) >> 4)
static ulong timestamp;
static ulong lastinc;
@@ -76,63 +66,51 @@ int timer_init(void)
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
- timer->tgcr = 0x06;
+ timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
lastinc = 0;
- timer->tcr = 0x80 << 16;
timestamp = 0;
+ timer->tcr = 2 << 22;
return(0);
}
void reset_timer(void)
{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return(get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
- lastinc = DIV(READ_TIMER);
+ timer->tcr = 0x0;
+ timer->tim34 = 0;
+ lastinc = 0;
timestamp = 0;
+ timer->tcr = 2 << 22;
}
-ulong get_timer_raw(void)
+static ulong get_timer_raw(void)
{
- ulong now = DIV(READ_TIMER);
+ ulong now = timer->tim34;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
- timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
-ulong get_timer_masked(void)
+ulong get_timer(ulong base)
+{
+ return(get_timer_raw() - base);
+}
+
+void set_timer(ulong t)
{
- return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
+ timestamp = t;
}
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -165,8 +143,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return(tbclk);
+ return CFG_HZ;
}
Index: uboot_davinci/include/configs/davinci_dvevm.h
===================================================================
--- uboot_davinci.orig/include/configs/davinci_dvevm.h
+++ uboot_davinci/include/configs/davinci_dvevm.h
@@ -58,7 +58,8 @@
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define TIM_CLK_DIV 16
+#define CFG_HZ_CLOCK (27000000/TIM_CLK_DIV) /* Timer clock freq */
#define CFG_HZ 1000
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
Index: uboot_davinci/include/configs/davinci_schmoogie.h
===================================================================
--- uboot_davinci.orig/include/configs/davinci_schmoogie.h
+++ uboot_davinci/include/configs/davinci_schmoogie.h
@@ -33,7 +33,8 @@
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define TIM_CLK_DIV 16
+#define CFG_HZ_CLOCK (27000000/TIM_CLK_DIV) /* Timer clock freq */
#define CFG_HZ 1000
/*=============*/
/* Memory Info */
Index: uboot_davinci/include/configs/davinci_sonata.h
===================================================================
--- uboot_davinci.orig/include/configs/davinci_sonata.h
+++ uboot_davinci/include/configs/davinci_sonata.h
@@ -58,7 +58,8 @@
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define TIM_CLK_DIV 16
+#define CFG_HZ_CLOCK (27000000/TIM_CLK_DIV) /* Timer clock freq */
#define CFG_HZ 1000
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
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