[U-Boot] [PATCH] ppc4xx: PPC44x MQ initialization

[Wolfgang Denk]

Dear Stefan Roese,

In message <1224240858-27235-1-git-send-email-sr at denx.de> you wrote:
> From: Yuri Tikhonov <yur at emcraft.com>
> 
> Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
> values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
> dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
> 
> Previously the appropriate initialization had been made in Linux, by the
> ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
> registers after normal operation has begun is not supported and could
> have unpredictable results.
> 
> Comment from Stefan: This patch doesn't change the resulting value of the
> MQ registers. It explicitly sets/clears all bits to the desired state which
> better documents the resulting register value instead of relying on pre-set
> default values.
> 
> Signed-off-by: Yuri Tikhonov <yur at emcraft.com>
> Signed-off-by: Stefan Roese <sr at denx.de>
> ---
> Yuri, I changed the patch description a little bit. Please let me know
> if you have any objections or if this is ok with you.
> 
> Thanks.
> 
>  cpu/ppc4xx/44x_spd_ddr2.c      |   10 ++++++----
>  include/asm-ppc/ppc4xx-sdram.h |    5 +++++
>  2 files changed, 11 insertions(+), 4 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

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