[U-Boot] [PATCH 02/19] ColdFire: Modules header files cleanup - 1
Tsi-Chung Liew
Tsi-Chung.Liew at freescale.com
Wed Oct 22 20:18:30 CEST 2008
From: TsiChung Liew <Tsi-Chung.Liew at freescale.com>
Consolidate ATA, ePORT and QSPI structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew at freescale.com>
---
include/asm-m68k/coldfire/ata.h | 79 +++++++++++++++++++++
include/asm-m68k/coldfire/dspi.h | 15 ++--
include/asm-m68k/coldfire/eport.h | 139 +++++++++++++++++++++++++++++++++++++
include/asm-m68k/coldfire/qspi.h | 111 +++++++++++++++++++++++++++++
include/asm-m68k/immap_5227x.h | 11 +---
include/asm-m68k/immap_5235.h | 19 +----
include/asm-m68k/immap_5249.h | 2 +
include/asm-m68k/immap_5253.h | 54 +--------------
include/asm-m68k/immap_5271.h | 3 +
include/asm-m68k/immap_5272.h | 16 ----
include/asm-m68k/immap_5275.h | 20 +-----
include/asm-m68k/immap_5282.h | 3 +
include/asm-m68k/immap_5329.h | 29 +-------
include/asm-m68k/immap_5445x.h | 62 +----------------
include/asm-m68k/immap_547x_8x.h | 2 +
include/asm-m68k/m5235.h | 91 ------------------------
include/asm-m68k/m5329.h | 51 --------------
include/asm-m68k/m5445x.h | 90 ------------------------
18 files changed, 359 insertions(+), 438 deletions(-)
create mode 100644 include/asm-m68k/coldfire/ata.h
create mode 100644 include/asm-m68k/coldfire/eport.h
create mode 100644 include/asm-m68k/coldfire/qspi.h
diff --git a/include/asm-m68k/coldfire/ata.h b/include/asm-m68k/coldfire/ata.h
new file mode 100644
index 0000000..3efd03a
--- /dev/null
+++ b/include/asm-m68k/coldfire/ata.h
@@ -0,0 +1,79 @@
+/*
+ * ATA Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* ATA */
+typedef struct atac {
+ /* PIO */
+ u8 toff; /* 0x00 */
+ u8 ton; /* 0x01 */
+ u8 t1; /* 0x02 */
+ u8 t2w; /* 0x03 */
+ u8 t2r; /* 0x04 */
+ u8 ta; /* 0x05 */
+ u8 trd; /* 0x06 */
+ u8 t4; /* 0x07 */
+ u8 t9; /* 0x08 */
+
+ /* DMA */
+ u8 tm; /* 0x09 */
+ u8 tn; /* 0x0A */
+ u8 td; /* 0x0B */
+ u8 tk; /* 0x0C */
+ u8 tack; /* 0x0D */
+ u8 tenv; /* 0x0E */
+ u8 trp; /* 0x0F */
+ u8 tzah; /* 0x10 */
+ u8 tmli; /* 0x11 */
+ u8 tdvh; /* 0x12 */
+ u8 tdzfs; /* 0x13 */
+ u8 tdvs; /* 0x14 */
+ u8 tcvh; /* 0x15 */
+ u8 tss; /* 0x16 */
+ u8 tcyc; /* 0x17 */
+
+ /* FIFO */
+ u32 fifo32; /* 0x18 */
+ u16 fifo16; /* 0x1C */
+ u8 rsvd0[2];
+ u8 ffill; /* 0x20 */
+ u8 rsvd1[3];
+
+ /* ATA */
+ u8 cr; /* 0x24 */
+ u8 rsvd2[3];
+ u8 isr; /* 0x28 */
+ u8 rsvd3[3];
+ u8 ier; /* 0x2C */
+ u8 rsvd4[3];
+ u8 icr; /* 0x30 */
+ u8 rsvd5[3];
+ u8 falarm; /* 0x34 */
+ u8 rsvd6[106];
+} atac_t;
+
+#endif /* __ATA_H__ */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
index 8327e1b..4b7d61e 100644
--- a/include/asm-m68k/coldfire/dspi.h
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -46,15 +46,14 @@ typedef struct dspi {
u32 dirsr;
u32 dtfr;
u32 drfr;
- u32 dtfdr0;
- u32 dtfdr1;
- u32 dtfdr2;
- u32 dtfdr3;
+#ifdef CONFIG_MCF547x_8x
+ u32 dtfdr[4];
u8 resv1[0x30];
- u32 drfdr0;
- u32 drfdr1;
- u32 drfdr2;
- u32 drfdr3;
+ u32 drfdr[4];
+#else
+ u32 dtfdr[16];
+ u32 drfdr[16];
+#endif
} dspi_t;
/* Bit definitions and macros for DMCR */
diff --git a/include/asm-m68k/coldfire/eport.h b/include/asm-m68k/coldfire/eport.h
new file mode 100644
index 0000000..1d1bf63
--- /dev/null
+++ b/include/asm-m68k/coldfire/eport.h
@@ -0,0 +1,139 @@
+/*
+ * Edge Port Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EPORT_H__
+#define __EPORT_H__
+
+/* Edge Port Module (EPORT) */
+typedef struct eport {
+#ifdef CONFIG_MCF547x_8x
+ u16 par; /* 0x00 */
+ u16 res0; /* 0x02 */
+ u8 ddr; /* 0x04 */
+ u8 ier; /* 0x05 */
+ u16 res1; /* 0x06 */
+ u8 dr; /* 0x08 */
+ u8 pdr; /* 0x09 */
+ u16 res2; /* 0x0A */
+ u8 fr; /* 0x0C */
+ u8 res3[3]; /* 0x0D */
+#else
+ u16 par; /* 0x00 Pin Assignment */
+ u8 ddr; /* 0x02 Data Direction */
+ u8 ier; /* 0x03 Interrupt Enable */
+ u8 dr; /* 0x04 Data */
+ u8 pdr; /* 0x05 Pin Data */
+ u8 fr; /* 0x06 Flag */
+ u8 res0;
+#endif
+} eport_t;
+
+/* EPPAR */
+#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
+#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
+#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
+#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
+#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
+#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
+#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
+#define EPORT_PAR_LEVEL (0)
+#define EPORT_PAR_RISING (1)
+#define EPORT_PAR_FALLING (2)
+#define EPORT_PAR_BOTH (3)
+#define EPORT_PAR_EPPA7_LEVEL (0x0000)
+#define EPORT_PAR_EPPA7_RISING (0x4000)
+#define EPORT_PAR_EPPA7_FALLING (0x8000)
+#define EPORT_PAR_EPPA7_BOTH (0xC000)
+#define EPORT_PAR_EPPA6_LEVEL (0x0000)
+#define EPORT_PAR_EPPA6_RISING (0x1000)
+#define EPORT_PAR_EPPA6_FALLING (0x2000)
+#define EPORT_PAR_EPPA6_BOTH (0x3000)
+#define EPORT_PAR_EPPA5_LEVEL (0x0000)
+#define EPORT_PAR_EPPA5_RISING (0x0400)
+#define EPORT_PAR_EPPA5_FALLING (0x0800)
+#define EPORT_PAR_EPPA5_BOTH (0x0C00)
+#define EPORT_PAR_EPPA4_LEVEL (0x0000)
+#define EPORT_PAR_EPPA4_RISING (0x0100)
+#define EPORT_PAR_EPPA4_FALLING (0x0200)
+#define EPORT_PAR_EPPA4_BOTH (0x0300)
+#define EPORT_PAR_EPPA3_LEVEL (0x0000)
+#define EPORT_PAR_EPPA3_RISING (0x0040)
+#define EPORT_PAR_EPPA3_FALLING (0x0080)
+#define EPORT_PAR_EPPA3_BOTH (0x00C0)
+#define EPORT_PAR_EPPA2_LEVEL (0x0000)
+#define EPORT_PAR_EPPA2_RISING (0x0010)
+#define EPORT_PAR_EPPA2_FALLING (0x0020)
+#define EPORT_PAR_EPPA2_BOTH (0x0030)
+#define EPORT_PAR_EPPA1_LEVEL (0x0000)
+#define EPORT_PAR_EPPA1_RISING (0x0004)
+#define EPORT_PAR_EPPA1_FALLING (0x0008)
+#define EPORT_PAR_EPPA1_BOTH (0x000C)
+
+/* EPDDR */
+#define EPORT_DDR_EPDD1 (0x02)
+#define EPORT_DDR_EPDD2 (0x04)
+#define EPORT_DDR_EPDD3 (0x08)
+#define EPORT_DDR_EPDD4 (0x10)
+#define EPORT_DDR_EPDD5 (0x20)
+#define EPORT_DDR_EPDD6 (0x40)
+#define EPORT_DDR_EPDD7 (0x80)
+
+/* EPIER */
+#define EPORT_IER_EPIE1 (0x02)
+#define EPORT_IER_EPIE2 (0x04)
+#define EPORT_IER_EPIE3 (0x08)
+#define EPORT_IER_EPIE4 (0x10)
+#define EPORT_IER_EPIE5 (0x20)
+#define EPORT_IER_EPIE6 (0x40)
+#define EPORT_IER_EPIE7 (0x80)
+
+/* EPDR */
+#define EPORT_DR_EPD1 (0x02)
+#define EPORT_DR_EPD2 (0x04)
+#define EPORT_DR_EPD3 (0x08)
+#define EPORT_DR_EPD4 (0x10)
+#define EPORT_DR_EPD5 (0x20)
+#define EPORT_DR_EPD6 (0x40)
+#define EPORT_DR_EPD7 (0x80)
+
+/* EPPDR */
+#define EPORT_PDR_EPPD1 (0x02)
+#define EPORT_PDR_EPPD2 (0x04)
+#define EPORT_PDR_EPPD3 (0x08)
+#define EPORT_PDR_EPPD4 (0x10)
+#define EPORT_PDR_EPPD5 (0x20)
+#define EPORT_PDR_EPPD6 (0x40)
+#define EPORT_PDR_EPPD7 (0x80)
+
+/* EPFR */
+#define EPORT_FR_EPF1 (0x02)
+#define EPORT_FR_EPF2 (0x04)
+#define EPORT_FR_EPF3 (0x08)
+#define EPORT_FR_EPF4 (0x10)
+#define EPORT_FR_EPF5 (0x20)
+#define EPORT_FR_EPF6 (0x40)
+#define EPORT_FR_EPF7 (0x80)
+
+#endif /* __EPORT_H__ */
diff --git a/include/asm-m68k/coldfire/qspi.h b/include/asm-m68k/coldfire/qspi.h
new file mode 100644
index 0000000..8bcd2e4
--- /dev/null
+++ b/include/asm-m68k/coldfire/qspi.h
@@ -0,0 +1,111 @@
+/*
+ * Queue Serial Peripheral Interface Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ u16 mr; /* 0x00 Mode */
+ u16 res1;
+ u16 dlyr; /* 0x04 Delay */
+ u16 res2;
+ u16 wr; /* 0x08 Wrap */
+ u16 res3;
+ u16 ir; /* 0x0C Interrupt */
+ u16 res4;
+ u16 ar; /* 0x10 Address */
+ u16 res5;
+ u16 dr; /* 0x14 Data */
+ u16 res6;
+} qspi_t;
+
+/* MR */
+#define QSPI_QMR_MSTR (0x8000)
+#define QSPI_QMR_DOHIE (0x4000)
+#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
+#define QSPI_QMR_BITS_MASK (0xC3FF)
+#define QSPI_QMR_BITS_8 (0x2000)
+#define QSPI_QMR_BITS_9 (0x2400)
+#define QSPI_QMR_BITS_10 (0x2800)
+#define QSPI_QMR_BITS_11 (0x2C00)
+#define QSPI_QMR_BITS_12 (0x3000)
+#define QSPI_QMR_BITS_13 (0x3400)
+#define QSPI_QMR_BITS_14 (0x3800)
+#define QSPI_QMR_BITS_15 (0x3C00)
+#define QSPI_QMR_BITS_16 (0x0000)
+#define QSPI_QMR_CPOL (0x0200)
+#define QSPI_QMR_CPHA (0x0100)
+#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
+#define QSPI_QMR_BAUD_MASK (0xFF00)
+
+/* DLYR */
+#define QSPI_QDLYR_SPE (0x8000)
+#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
+#define QSPI_QDLYR_QCD_MASK (0x80FF)
+#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
+#define QSPI_QDLYR_DTL_MASK (0xFF00)
+
+/* WR */
+#define QSPI_QWR_HALT (0x8000)
+#define QSPI_QWR_WREN (0x4000)
+#define QSPI_QWR_WRTO (0x2000)
+#define QSPI_QWR_CSIV (0x1000)
+#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
+#define QSPI_QWR_ENDQP_MASK (0xF0FF)
+#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
+#define QSPI_QWR_CPTQP_MASK (0xFF0F)
+#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
+#define QSPI_QWR_NEWQP_MASK (0xFFF0)
+
+/* IR */
+#define QSPI_QIR_WCEFB (0x8000)
+#define QSPI_QIR_ABRTB (0x4000)
+#define QSPI_QIR_ABRTL (0x1000)
+#define QSPI_QIR_WCEFE (0x0800)
+#define QSPI_QIR_ABRTE (0x0400)
+#define QSPI_QIR_SPIFE (0x0100)
+#define QSPI_QIR_WCEF (0x0008)
+#define QSPI_QIR_ABRT (0x0004)
+#define QSPI_QIR_SPIF (0x0001)
+
+/* AR */
+#define QSPI_QAR_ADDR(x) ((x)&0x003F)
+#define QSPI_QAR_ADDR_MASK (0xFFC0)
+#define QSPI_QAR_TRANS (0x0000)
+#define QSPI_QAR_RECV (0x0010)
+#define QSPI_QAR_CMD (0x0020)
+
+/* DR */
+#define QSPI_QDR_CONT (0x8000)
+#define QSPI_QDR_BITSE (0x4000)
+#define QSPI_QDR_DT (0x2000)
+#define QSPI_QDR_DSCK (0x1000)
+#define QSPI_QDR_QSPI_CS3 (0x0800)
+#define QSPI_QDR_QSPI_CS2 (0x0400)
+#define QSPI_QDR_QSPI_CS1 (0x0200)
+#define QSPI_QDR_QSPI_CS0 (0x0100)
+
+#endif /* __QSPI_H__ */
diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h
index 83da3d5..df1ec4a 100644
--- a/include/asm-m68k/immap_5227x.h
+++ b/include/asm-m68k/immap_5227x.h
@@ -69,6 +69,7 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/ssi.h>
@@ -162,16 +163,6 @@ typedef struct iack {
u8 gl7iack;
} iack_t;
-/* Edge Port Module (EPORT) */
-typedef struct eport {
- u16 eppar;
- u8 epddr;
- u8 epier;
- u8 epdr;
- u8 eppdr;
- u8 epfr;
-} eport_t;
-
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h
index 3ef0321..dfab416 100644
--- a/include/asm-m68k/immap_5235.h
+++ b/include/asm-m68k/immap_5235.h
@@ -63,6 +63,9 @@
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
+
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
@@ -155,22 +158,6 @@ typedef struct fbcs_ctrl {
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
-/* QSPI module registers */
-typedef struct qspi_ctrl {
- u16 qmr; /* Mode register */
- u16 res1;
- u16 qdlyr; /* Delay register */
- u16 res2;
- u16 qwr; /* Wrap register */
- u16 res3;
- u16 qir; /* Interrupt register */
- u16 res4;
- u16 qar; /* Address register */
- u16 res5;
- u16 qdr; /* Data register */
- u16 res6;
-} qspi_t;
-
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h
index 6b57ba7..f4fedfd 100644
--- a/include/asm-m68k/immap_5249.h
+++ b/include/asm-m68k/immap_5249.h
@@ -32,4 +32,6 @@
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
+#include <asm/coldfire/qspi.h>
+
#endif /* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
index 4e3a481..fa09923 100644
--- a/include/asm-m68k/immap_5253.h
+++ b/include/asm-m68k/immap_5253.h
@@ -39,57 +39,7 @@
#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
-/*********************************************************************
-* ATA Module (ATAC)
-*********************************************************************/
-
-/* Register read/write struct */
-typedef struct atac {
- /* PIO */
- u8 toff; /* 0x00 */
- u8 ton; /* 0x01 */
- u8 t1; /* 0x02 */
- u8 t2w; /* 0x03 */
- u8 t2r; /* 0x04 */
- u8 ta; /* 0x05 */
- u8 trd; /* 0x06 */
- u8 t4; /* 0x07 */
- u8 t9; /* 0x08 */
-
- /* DMA */
- u8 tm; /* 0x09 */
- u8 tn; /* 0x0A */
- u8 td; /* 0x0B */
- u8 tk; /* 0x0C */
- u8 tack; /* 0x0D */
- u8 tenv; /* 0x0E */
- u8 trp; /* 0x0F */
- u8 tzah; /* 0x10 */
- u8 tmli; /* 0x11 */
- u8 tdvh; /* 0x12 */
- u8 tdzfs; /* 0x13 */
- u8 tdvs; /* 0x14 */
- u8 tcvh; /* 0x15 */
- u8 tss; /* 0x16 */
- u8 tcyc; /* 0x17 */
-
- /* FIFO */
- u32 fifo32; /* 0x18 */
- u16 fifo16; /* 0x1C */
- u8 rsvd0[2];
- u8 ffill; /* 0x20 */
- u8 rsvd1[3];
-
- /* ATA */
- u8 cr; /* 0x24 */
- u8 rsvd2[3];
- u8 isr; /* 0x28 */
- u8 rsvd3[3];
- u8 ier; /* 0x2C */
- u8 rsvd4[3];
- u8 icr; /* 0x30 */
- u8 rsvd5[3];
- u8 falarm; /* 0x34 */
-} atac_t;
+#include <asm/coldfire/ata.h>
+#include <asm/coldfire/qspi.h>
#endif /* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h
index 462d5f2..8483501 100644
--- a/include/asm-m68k/immap_5271.h
+++ b/include/asm-m68k/immap_5271.h
@@ -63,6 +63,9 @@
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
+
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h
index b106289..d904053 100644
--- a/include/asm-m68k/immap_5272.h
+++ b/include/asm-m68k/immap_5272.h
@@ -104,22 +104,6 @@ typedef struct gpio_ctrl {
uchar res2[4];
} gpio_t;
-/* QSPI module registers */
-typedef struct qspi_ctrl {
- ushort qspi_qmr;
- uchar res1[2];
- ushort qspi_qdlyr;
- uchar res2[2];
- ushort qspi_qwr;
- uchar res3[2];
- ushort qspi_qir;
- uchar res4[2];
- ushort qspi_qar;
- uchar res5[2];
- ushort qspi_qdr;
- uchar res6[10];
-} qspi_t;
-
/* PWM module registers */
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
index 495010b..72846fc 100644
--- a/include/asm-m68k/immap_5275.h
+++ b/include/asm-m68k/immap_5275.h
@@ -66,6 +66,9 @@
#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
+
/* System configuration registers
*/
typedef struct sys_ctrl {
@@ -163,23 +166,6 @@ typedef struct dma_ctrl {
u32 dcr;
} dma_t;
-/* QSPI module registers, offset 0x340
- */
-typedef struct qspi_ctrl {
- u16 qmr;
- u8 res1[2];
- u16 qdlyr;
- u8 res2[2];
- u16 qwr;
- u8 res3[2];
- u16 qir;
- u8 res4[2];
- u16 qar;
- u8 res5[2];
- u16 qdr;
- u8 res6[2];
-} qspi_t;
-
/* Interrupt module registers, offset 0xc00
*/
typedef struct int_ctrl {
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index e96463b..417502d 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -62,6 +62,9 @@
#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
+
/* System Control Module */
typedef struct scm_ctrl {
u32 ipsbar;
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 7678406..88f9b20 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -70,6 +70,8 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/ssi.h>
@@ -282,22 +284,6 @@ typedef struct intgack_ctrl1 {
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
-/* QSPI module registers */
-typedef struct qspi_ctrl {
- u16 qmr; /* Mode register */
- u16 res1;
- u16 qdlyr; /* Delay register */
- u16 res2;
- u16 qwr; /* Wrap register */
- u16 res3;
- u16 qir; /* Interrupt register */
- u16 res4;
- u16 qar; /* Address register */
- u16 res5;
- u16 qdr; /* Data register */
- u16 res6;
-} qspi_t;
-
/* PWM module registers */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable Register */
@@ -338,17 +324,6 @@ typedef struct pwm_ctrl {
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
-/* Edge Port module registers */
-typedef struct eport_ctrl {
- u16 par; /* 0x00 Pin Assignment Register */
- u8 ddar; /* 0x02 Data Direction Register */
- u8 ier; /* 0x03 Interrupt Enable Register */
- u8 dr; /* 0x04 Data Register */
- u8 pdr; /* 0x05 Pin Data Register */
- u8 fr; /* 0x06 Flag_Register */
- u8 res1;
-} eport_t;
-
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
index ef8930e..38b767f 100644
--- a/include/asm-m68k/immap_5445x.h
+++ b/include/asm-m68k/immap_5445x.h
@@ -69,62 +69,14 @@
#define MMAP_USBEHCI 0xFC0B0140
#define MMAP_USBOTG 0xFC0B01A0
+#include <asm/coldfire/ata.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/ssi.h>
-/* ATA */
-typedef struct atac {
- /* PIO */
- u8 toff; /* 0x00 */
- u8 ton; /* 0x01 */
- u8 t1; /* 0x02 */
- u8 t2w; /* 0x03 */
- u8 t2r; /* 0x04 */
- u8 ta; /* 0x05 */
- u8 trd; /* 0x06 */
- u8 t4; /* 0x07 */
- u8 t9; /* 0x08 */
-
- /* DMA */
- u8 tm; /* 0x09 */
- u8 tn; /* 0x0A */
- u8 td; /* 0x0B */
- u8 tk; /* 0x0C */
- u8 tack; /* 0x0D */
- u8 tenv; /* 0x0E */
- u8 trp; /* 0x0F */
- u8 tzah; /* 0x10 */
- u8 tmli; /* 0x11 */
- u8 tdvh; /* 0x12 */
- u8 tdzfs; /* 0x13 */
- u8 tdvs; /* 0x14 */
- u8 tcvh; /* 0x15 */
- u8 tss; /* 0x16 */
- u8 tcyc; /* 0x17 */
-
- /* FIFO */
- u32 fifo32; /* 0x18 */
- u16 fifo16; /* 0x1C */
- u8 rsvd0[2];
- u8 ffill; /* 0x20 */
- u8 rsvd1[3];
-
- /* ATA */
- u8 cr; /* 0x24 */
- u8 rsvd2[3];
- u8 isr; /* 0x28 */
- u8 rsvd3[3];
- u8 ier; /* 0x2C */
- u8 rsvd4[3];
- u8 icr; /* 0x30 */
- u8 rsvd5[3];
- u8 falarm; /* 0x34 */
- u8 rsvd6[106];
-} atac_t;
-
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
@@ -214,16 +166,6 @@ typedef struct iack {
u8 gl7iack;
} iack_t;
-/* Edge Port Module (EPORT) */
-typedef struct eport {
- u16 eppar;
- u8 epddr;
- u8 epier;
- u8 epdr;
- u8 eppdr;
- u8 epfr;
-} eport_t;
-
/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
diff --git a/include/asm-m68k/immap_547x_8x.h b/include/asm-m68k/immap_547x_8x.h
index c221936..f11b61a 100644
--- a/include/asm-m68k/immap_547x_8x.h
+++ b/include/asm-m68k/immap_547x_8x.h
@@ -57,6 +57,8 @@
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
typedef struct siu {
diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h
index b98b452..e4880c0 100644
--- a/include/asm-m68k/m5235.h
+++ b/include/asm-m68k/m5235.h
@@ -203,54 +203,6 @@
#define FBCS_CSCR_SWWS(x) ((x)&0x07)
/*********************************************************************
-* Queued Serial Peripheral Interface (QSPI)
-*********************************************************************/
-/* Bit definitions and macros for QSPI_QMR */
-#define QSPI_QMR_MSTR (0x8000)
-#define QSPI_QMR_DOHIE (0x4000)
-#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
-#define QSPI_QMR_CPOL (0x0200)
-#define QSPI_QMR_CPHA (0x0100)
-#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QDLYR */
-#define QSPI_QDLYR_SPE (0x8000)
-#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
-#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QWR */
-#define QSPI_QWR_HALT (0x8000)
-#define QSPI_QWR_WREN (0x4000)
-#define QSPI_QWR_WRTO (0x2000)
-#define QSPI_QWR_CSIV (0x1000)
-#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
-#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
-
-/* Bit definitions and macros for QSPI_QIR */
-#define QSPI_QIR_WCEFB (0x8000)
-#define QSPI_QIR_ABRTB (0x4000)
-#define QSPI_QIR_ABRTL (0x1000)
-#define QSPI_QIR_WCEFE (0x0800)
-#define QSPI_QIR_ABRTE (0x0400)
-#define QSPI_QIR_SPIFE (0x0100)
-#define QSPI_QIR_WCEF (0x0008)
-#define QSPI_QIR_ABRT (0x0004)
-#define QSPI_QIR_SPIF (0x0001)
-
-/* Bit definitions and macros for QSPI_QAR */
-#define QSPI_QAR_ADDR(x) ((x)&0x003F)
-
-/* Bit definitions and macros for QSPI_QDR */
-#define QSPI_QDR_CONT (0x8000)
-#define QSPI_QDR_BITSE (0x4000)
-#define QSPI_QDR_DT (0x2000)
-#define QSPI_QDR_DSCK (0x1000)
-#define QSPI_QDR_QSPI_CS3 (0x0800)
-#define QSPI_QDR_QSPI_CS2 (0x0400)
-#define QSPI_QDR_QSPI_CS1 (0x0200)
-#define QSPI_QDR_QSPI_CS0 (0x0100)
-
-/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
@@ -758,49 +710,6 @@
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
- * Edge Port
-*********************************************************************/
-#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
-#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
-#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
-#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
-#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
-#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
-#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
-
-#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
-#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
-#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
-#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
-#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
-#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
-#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
-
-#define EPORT_EPIER_EPIE7 (0x80)
-#define EPORT_EPIER_EPIE6 (0x40)
-#define EPORT_EPIER_EPIE5 (0x20)
-#define EPORT_EPIER_EPIE4 (0x10)
-#define EPORT_EPIER_EPIE3 (0x08)
-#define EPORT_EPIER_EPIE2 (0x04)
-#define EPORT_EPIER_EPIE1 (0x02)
-
-#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
-#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
-#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
-#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
-#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
-#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
-#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
-
-#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
-#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
-#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
-#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
-#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
-#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
-#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
-
-/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WTM_WCR */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index c1669dc..b05da52 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -507,57 +507,6 @@
#define INTC_ICR_IL(x) ((x)&0x07)
/*********************************************************************
-* Queued Serial Peripheral Interface (QSPI)
-*********************************************************************/
-/* Bit definitions and macros for QSPI_QMR */
-#define QSPI_QMR_MSTR (0x8000)
-#define QSPI_QMR_DOHIE (0x4000)
-#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
-#define QSPI_QMR_CPOL (0x0200)
-#define QSPI_QMR_CPHA (0x0100)
-#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QDLYR */
-#define QSPI_QDLYR_SPE (0x8000)
-#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
-#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QWR */
-#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
-#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
-#define QSPI_QWR_CSIV (0x1000)
-#define QSPI_QWR_WRTO (0x2000)
-#define QSPI_QWR_WREN (0x4000)
-#define QSPI_QWR_HALT (0x8000)
-
-/* Bit definitions and macros for QSPI_QIR */
-#define QSPI_QIR_WCEFB (0x8000)
-#define QSPI_QIR_ABRTB (0x4000)
-#define QSPI_QIR_ABRTL (0x1000)
-#define QSPI_QIR_WCEFE (0x0800)
-#define QSPI_QIR_ABRTE (0x0400)
-#define QSPI_QIR_SPIFE (0x0100)
-#define QSPI_QIR_WCEF (0x0008)
-#define QSPI_QIR_ABRT (0x0004)
-#define QSPI_QIR_SPIF (0x0001)
-
-/* Bit definitions and macros for QSPI_QAR */
-#define QSPI_QAR_ADDR(x) ((x)&0x003F)
-#define QSPI_QAR_TRANS (0x0000)
-#define QSPI_QAR_RECV (0x0010)
-#define QSPI_QAR_CMD (0x0020)
-
-/* Bit definitions and macros for QSPI_QDR */
-#define QSPI_QDR_CONT (0x8000)
-#define QSPI_QDR_BITSE (0x4000)
-#define QSPI_QDR_DT (0x2000)
-#define QSPI_QDR_DSCK (0x1000)
-#define QSPI_QDR_QSPI_CS3 (0x0800)
-#define QSPI_QDR_QSPI_CS2 (0x0400)
-#define QSPI_QDR_QSPI_CS1 (0x0200)
-#define QSPI_QDR_QSPI_CS0 (0x0100)
-
-/*********************************************************************
* Pulse Width Modulation (PWM)
*********************************************************************/
/* Bit definitions and macros for PWM_E */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index 7fcf4ef..69d4aac 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -344,96 +344,6 @@
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
-* Edge Port Module (EPORT)
-*********************************************************************/
-
-/* Bit definitions and macros for EPPAR */
-#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
-#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
-#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
-#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
-#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
-#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
-#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
-#define EPORT_EPPAR_LEVEL (0)
-#define EPORT_EPPAR_RISING (1)
-#define EPORT_EPPAR_FALLING (2)
-#define EPORT_EPPAR_BOTH (3)
-#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA7_RISING (0x4000)
-#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
-#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
-#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA6_RISING (0x1000)
-#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
-#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
-#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA5_RISING (0x0400)
-#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
-#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
-#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA4_RISING (0x0100)
-#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
-#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
-#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA3_RISING (0x0040)
-#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
-#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
-#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA2_RISING (0x0010)
-#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
-#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
-#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
-#define EPORT_EPPAR_EPPA1_RISING (0x0004)
-#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
-#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
-
-/* Bit definitions and macros for EPDDR */
-#define EPORT_EPDDR_EPDD1 (0x02)
-#define EPORT_EPDDR_EPDD2 (0x04)
-#define EPORT_EPDDR_EPDD3 (0x08)
-#define EPORT_EPDDR_EPDD4 (0x10)
-#define EPORT_EPDDR_EPDD5 (0x20)
-#define EPORT_EPDDR_EPDD6 (0x40)
-#define EPORT_EPDDR_EPDD7 (0x80)
-
-/* Bit definitions and macros for EPIER */
-#define EPORT_EPIER_EPIE1 (0x02)
-#define EPORT_EPIER_EPIE2 (0x04)
-#define EPORT_EPIER_EPIE3 (0x08)
-#define EPORT_EPIER_EPIE4 (0x10)
-#define EPORT_EPIER_EPIE5 (0x20)
-#define EPORT_EPIER_EPIE6 (0x40)
-#define EPORT_EPIER_EPIE7 (0x80)
-
-/* Bit definitions and macros for EPDR */
-#define EPORT_EPDR_EPD1 (0x02)
-#define EPORT_EPDR_EPD2 (0x04)
-#define EPORT_EPDR_EPD3 (0x08)
-#define EPORT_EPDR_EPD4 (0x10)
-#define EPORT_EPDR_EPD5 (0x20)
-#define EPORT_EPDR_EPD6 (0x40)
-#define EPORT_EPDR_EPD7 (0x80)
-
-/* Bit definitions and macros for EPPDR */
-#define EPORT_EPPDR_EPPD1 (0x02)
-#define EPORT_EPPDR_EPPD2 (0x04)
-#define EPORT_EPPDR_EPPD3 (0x08)
-#define EPORT_EPPDR_EPPD4 (0x10)
-#define EPORT_EPPDR_EPPD5 (0x20)
-#define EPORT_EPPDR_EPPD6 (0x40)
-#define EPORT_EPPDR_EPPD7 (0x80)
-
-/* Bit definitions and macros for EPFR */
-#define EPORT_EPFR_EPF1 (0x02)
-#define EPORT_EPFR_EPF2 (0x04)
-#define EPORT_EPFR_EPF3 (0x08)
-#define EPORT_EPFR_EPF4 (0x10)
-#define EPORT_EPFR_EPF5 (0x20)
-#define EPORT_EPFR_EPF6 (0x40)
-#define EPORT_EPFR_EPF7 (0x80)
-
-/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
--
1.5.6.4
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