[U-Boot] [PATCH 04/13 v4] ARM: OMAP3: Add ARM Cortex A8 common directory
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Sun Oct 26 17:52:46 CET 2008
On 21:27 Fri 17 Oct , dirk.behme at googlemail.com wrote:
> From: Dirk Behme <dirk.behme at gmail.com>
>
> Add ARM Cortex A8 common directory
>
> Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
>
> ---
> cpu/arm_cortexa8/Makefile | 43 +++
> cpu/arm_cortexa8/config.mk | 36 +++
> cpu/arm_cortexa8/cpu.c | 221 +++++++++++++++++++
> cpu/arm_cortexa8/start.S | 522 +++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 822 insertions(+)
>
> Index: u-boot-arm/cpu/arm_cortexa8/cpu.c
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/cpu.c
> @@ -0,0 +1,221 @@
> +/*
> + * (C) Copyright 2008 Texas Insturments
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger at sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * CPU specific code
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +
> +#ifdef CONFIG_USE_IRQ
> +DECLARE_GLOBAL_DATA_PTR;
> +#endif
> +
> +#ifndef CONFIG_L2_OFF
> +void l2cache_disable(void);
> +#endif
> +
> +/* read co-processor 15, register #1 (control register) */
> +static unsigned long read_p15_c1(void)
> +{
> + unsigned long value;
> +
> + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
> + @ read control reg\n":"=r"(value)
> + ::"memory");
> + return value;
> +}
> +
> +/* write to co-processor 15, register #1 (control register) */
> +static void write_p15_c1(unsigned long value)
> +{
> + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
> + @ write it back\n"::"r"(value)
> + : "memory");
> +
> + read_p15_c1();
> +}
> +
> +static void cp_delay(void)
> +{
> + volatile int i;
> +
> + /* Many OMAP regs need at least 2 nops */
> + for (i = 0; i < 100; i++) ;
> +}
> +
> +/* See also ARM Ref. Man. */
> +#define C1_MMU (1<<0) /* mmu off/on */
> +#define C1_ALIGN (1<<1) /* alignment faults off/on */
> +#define C1_DC (1<<2) /* dcache off/on */
> +#define C1_WB (1<<3) /* merging write buffer on/off */
> +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
> +#define C1_SYS_PROT (1<<8) /* system protection */
> +#define C1_ROM_PROT (1<<9) /* ROM protection */
> +#define C1_IC (1<<12) /* icache off/on */
> +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
> +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
> +
> +int cpu_init(void)
> +{
> + /*
> + * setup up stacks if necessary
> + */
> +#ifdef CONFIG_USE_IRQ
> + IRQ_STACK_START =
> + _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
> + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
> +#endif
> + return 0;
> +}
> +
> +int cleanup_before_linux(void)
> +{
> + unsigned int i;
> +
> + /*
> + * this function is called just before we call linux
> + * it prepares the processor for linux
> + *
> + * we turn off caches etc ...
> + */
> + disable_interrupts();
> +
> + /* turn off I/D-cache */
> + asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
> + i &= ~(C1_DC | C1_IC);
> + asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i));
> +
please do as done in cpu/arm1176/cpu.c
create i/dcache_disable() and cache_flush(), etc...
> + /* invalidate I-cache */
> + arm_cache_flush();
> +#ifndef CONFIG_L2_OFF
> + /* turn off L2 cache */
> + l2cache_disable();
> + /* invalidate L2 cache also */
> + v7_flush_dcache_all(get_device_type());
> +#endif
> + i = 0;
> + /* mem barrier to sync up things */
> + asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
> +
> +#ifndef CONFIG_L2_OFF
> + l2cache_enable();
> +#endif
> +
> + return 0;
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
> +{
> + disable_interrupts();
> + reset_cpu(0);
> +
> + /* NOTREACHED */
> + return 0;
> +}
> +
> +void icache_enable(void)
> +{
> + ulong reg;
> +
> + reg = read_p15_c1(); /* get control reg. */
> + cp_delay();
> + write_p15_c1(reg | C1_IC);
> +}
> +
> +void icache_disable(void)
> +{
> + ulong reg;
> +
> + reg = read_p15_c1();
> + cp_delay();
> + write_p15_c1(reg & ~C1_IC);
> +}
> +
> +void l2cache_enable()
> +{
> + unsigned long i;
> + volatile unsigned int j;
> +
> + /* ES2 onwards we can disable/enable L2 ourselves */
> + if (get_cpu_rev() == CPU_3430_ES2) {
> + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
> + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> + } else {
> + /* Save r0, r12 and restore them after usage */
> + __asm__ __volatile__("mov %0, r12":"=r"(j));
> + __asm__ __volatile__("mov %0, r0":"=r"(i));
> +
> + /* GP Device ROM code API usage here */
> + /* r12 = AUXCR Write function and r0 value */
> + __asm__ __volatile__("mov r12, #0x3");
> + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> + __asm__ __volatile__("orr r0, r0, #0x2");
> + /* SMI instruction to call ROM Code API */
> + __asm__ __volatile__(".word 0xE1600070");
> + __asm__ __volatile__("mov r0, %0":"=r"(i));
> + __asm__ __volatile__("mov r12, %0":"=r"(j));
> + }
> +
> +}
> +
> +void l2cache_disable()
> +{
> + unsigned long i;
> + volatile unsigned int j;
> +
> + /* ES2 onwards we can disable/enable L2 ourselves */
> + if (get_cpu_rev() == CPU_3430_ES2) {
> + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
> + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> + } else {
> + /* Save r0, r12 and restore them after usage */
> + __asm__ __volatile__("mov %0, r12":"=r"(j));
> + __asm__ __volatile__("mov %0, r0":"=r"(i));
> +
> + /* GP Device ROM code API usage here */
> + /* r12 = AUXCR Write function and r0 value */
> + __asm__ __volatile__("mov r12, #0x3");
> + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> + __asm__ __volatile__("bic r0, r0, #0x2");
> + /* SMI instruction to call ROM Code API */
> + __asm__ __volatile__(".word 0xE1600070");
> + __asm__ __volatile__("mov r0, %0":"=r"(i));
> + __asm__ __volatile__("mov r12, %0":"=r"(j));
> + }
> +}
> +
> +int icache_status(void)
> +{
> + return (read_p15_c1() & C1_IC) != 0;
> +}
> Index: u-boot-arm/cpu/arm_cortexa8/Makefile
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/Makefile
> @@ -0,0 +1,43 @@
> +#
> +# (C) Copyright 2000-2003
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = lib$(CPU).a
add $(obj)
> +
> +START := start.o
> +OBJS := cpu.o
> +
please add
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
> +all: .depend $(START) $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(AR) crv $@ $(OBJS)
please replace crv with $(ARFLAGS)
> +
> +#########################################################################
> +
> +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
> + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
please replace by
include $(SRCTREE)/rules.mk
> +
> +sinclude .depend
> +
> +#########################################################################
> \ No newline at end of file
> Index: u-boot-arm/cpu/arm_cortexa8/config.mk
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/config.mk
> @@ -0,0 +1,36 @@
> +#
> +# (C) Copyright 2002
> +# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
^
whitespace please remove
> + -msoft-float
> +
> +# Make ARMv5 to allow more compilers to work, even though its v7a.
> +PLATFORM_CPPFLAGS += -march=armv5
> +# =========================================================================
> +#
> +# Supply options according to compiler version
> +#
> +# =========================================================================
> +PLATFORM_CPPFLAGS +=$(call cc-option)
> +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
> +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
> + $(call cc-option,-malignment-traps,))
> \ No newline at end of file
> Index: u-boot-arm/cpu/arm_cortexa8/start.S
> ===================================================================
> --- /dev/null
> +++ u-boot-arm/cpu/arm_cortexa8/start.S
> @@ -0,0 +1,522 @@
> +/*
> + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
^
whitespace please remove
> + *
> + * Copyright (c) 2004 Texas Instruments <r-woodruff2 at ti.com>
^
whitespace please remove
> + *
> + * Copyright (c) 2001 Marius Gröger <mag at sysgo.de>
^
whitespace please remove
> + * Copyright (c) 2002 Alex Züpke <azu at sysgo.de>
^
whitespace please remove
> + * Copyright (c) 2002 Gary Jennejohn <gj at denx.de>
^
whitespace please remove
> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2 at ti.com>
^
whitespace please remove
> + * Copyright (c) 2003 Kshitij <kshitij at ti.com>
^
whitespace please remove
> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim at ti.com>
^
whitespace please remove
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +
> +.globl _start
> +_start: b reset
> + ldr pc, _undefined_instruction
> + ldr pc, _software_interrupt
> + ldr pc, _prefetch_abort
> + ldr pc, _data_abort
> + ldr pc, _not_used
> + ldr pc, _irq
> + ldr pc, _fiq
> +
> +_undefined_instruction: .word undefined_instruction
> +_software_interrupt: .word software_interrupt
> +_prefetch_abort: .word prefetch_abort
> +_data_abort: .word data_abort
> +_not_used: .word not_used
> +_irq: .word irq
> +_fiq: .word fiq
> +_pad: .word 0x12345678 /* now 16*4=64 */
> +.global _end_vect
> +_end_vect:
> +
> + .balignl 16,0xdeadbeef
> +/*************************************************************************
> + *
> + * Startup Code (reset vector)
> + *
> + * do important init only if we don't start from memory!
> + * setup Memory and board specific bits prior to relocation.
> + * relocate armboot to ram
> + * setup stack
> + *
> + *************************************************************************/
> +
> +_TEXT_BASE:
> + .word TEXT_BASE
> +
> +.globl _armboot_start
> +_armboot_start:
> + .word _start
> +
> +/*
> + * These are defined in the board-specific linker script.
> + */
> +.globl _bss_start
> +_bss_start:
> + .word __bss_start
> +
> +.globl _bss_end
> +_bss_end:
> + .word _end
> +
> +#ifdef CONFIG_USE_IRQ
> +/* IRQ stack memory (calculated at run-time) */
> +.globl IRQ_STACK_START
> +IRQ_STACK_START:
> + .word 0x0badc0de
please macro instead of value on all
> +
> +/* IRQ stack memory (calculated at run-time) */
> +.globl FIQ_STACK_START
> +FIQ_STACK_START:
> + .word 0x0badc0de
> +#endif
> +
> +/*
> + * the actual reset code
> + */
> +
> +reset:
> + /*
> + * set the cpu to SVC32 mode
> + */
> + mrs r0,cpsr
> + bic r0,r0,#0x1f
> + orr r0,r0,#0xd3
> + msr cpsr,r0
> +
> +#if (CONFIG_OMAP34XX)
> + /* Copy vectors to mask ROM indirect addr */
> + adr r0, _start @ r0 <- current position of code
> + add r0, r0, #4 @ skip reset vector
> + mov r2, #64 @ r2 <- size to copy
> + add r2, r0, r2 @ r2 <- source end address
> + mov r1, #SRAM_OFFSET0 @ build vect addr
> + mov r3, #SRAM_OFFSET1
> + add r1, r1, r3
> + mov r3, #SRAM_OFFSET2
> + add r1, r1, r3
> +next:
> + ldmia r0!, {r3-r10} @ copy from source address [r0]
please add space between '-'
> + stmia r1!, {r3-r10} @ copy to target address [r1]
> + cmp r0, r2 @ until source end address [r2]
> + bne next @ loop until equal */
> +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
> + /* No need to copy/exec the clock code - DPLL adjust already done
> + * in NAND/oneNAND Boot.
> + */
> + bl cpy_clk_code @ put dpll adjust code behind vectors
> +#endif /* NAND Boot */
> +#endif
> + /* the mask ROM code should have PLL and others stable */
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> + bl cpu_init_crit
> +#endif
> +
> +#ifndef CONFIG_SKIP_RELOCATE_UBOOT
> +relocate: @ relocate U-Boot to RAM
> + adr r0, _start @ r0 <- current position of code
> + ldr r1, _TEXT_BASE @ test if we run from flash or RAM
> + cmp r0, r1 @ don't reloc during debug
> + beq stack_setup
> +
> + ldr r2, _armboot_start
> + ldr r3, _bss_start
> + sub r2, r3, r2 @ r2 <- size of armboot
> + add r2, r0, r2 @ r2 <- source end address
> +
> +copy_loop: @ copy 32 bytes at a time
> + ldmia r0!, {r3-r10} @ copy from source address [r0]
> + stmia r1!, {r3-r10} @ copy to target address [r1]
> + cmp r0, r2 @ until source end addreee [r2]
> + ble copy_loop
> +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
> +
> + /* Set up the stack */
> +stack_setup:
> + ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
> + sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
> + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
> +#ifdef CONFIG_USE_IRQ
> + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
> +#endif
> + sub sp, r0, #12 @ leave 3 words for abort-stack
> + and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
> +
> + /* Clear BSS (if any). Is below tx (watch load addr - need space) */
> +clear_bss:
> + ldr r0, _bss_start @ find start of bss segment
> + ldr r1, _bss_end @ stop here
> + mov r2, #0x00000000 @ clear value
^
whitespace please remove
> +clbss_l:
> + str r2, [r0] @ clear BSS location
> + cmp r0, r1 @ are we at the end yet
> + add r0, r0, #4 @ increment clear index pointer
> + bne clbss_l @ keep clearing till at end
> +
> + ldr pc, _start_armboot @ jump to C code
> +
> +_start_armboot: .word start_armboot
> +
> +
> +/*************************************************************************
> + *
> + * CPU_init_critical registers
> + *
> + * setup important registers
> + * setup memory timing
> + *
> + *************************************************************************/
> +cpu_init_crit:
> + /*
> + * Invalidate L1 I/D
> + */
> + mov r0, #0 @ set up for MCR
> + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
> + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
why create function that could be call from c also
> +
> + /*
> + * disable MMU stuff and caches
> + */
> + mrc p15, 0, r0, c1, c0, 0
> + bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
> + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
> + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
> + orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
> + mcr p15, 0, r0, c1, c0, 0
why create function that could be call from c also
this could be availlable for all cache/mmu/interruptions function
> +
> + /*
> + * Jump to board specific initialization...
> + * The Mask ROM will have already initialized
> + * basic memory. Go here to bump up clock rate and handle
> + * wake up conditions.
> + */
> + mov ip, lr @ persevere link reg across call
> + bl lowlevel_init @ go setup pll,mux,memory
> + mov lr, ip @ restore link
> + mov pc, lr @ back to my caller
> +/*
> + *************************************************************************
> + *
> + * Interrupt handling
> + *
> + *************************************************************************
> + */
> +@
> +@ IRQ stack frame.
> +@
> +#define S_FRAME_SIZE 72
> +
> +#define S_OLD_R0 68
> +#define S_PSR 64
> +#define S_PC 60
> +#define S_LR 56
> +#define S_SP 52
> +
> +#define S_IP 48
> +#define S_FP 44
> +#define S_R10 40
> +#define S_R9 36
> +#define S_R8 32
> +#define S_R7 28
> +#define S_R6 24
> +#define S_R5 20
> +#define S_R4 16
> +#define S_R3 12
> +#define S_R2 8
> +#define S_R1 4
> +#define S_R0 0
> +
> +#define MODE_SVC 0x13
> +#define I_BIT 0x80
> +
> +/*
> + * use bad_save_user_regs for abort/prefetch/undef/swi ...
> + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
> + */
> +
> + .macro bad_save_user_regs
> + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
> + @ user stack
> + stmia sp, {r0 - r12} @ Save user registers (now in
> + @ svc mode) r0-r12
> +
> + ldr r2, _armboot_start
> + sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
> + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort
please add space between '+'
Best Regards,
J.
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