[U-Boot] [PATCH 38/42] Blackfin: bf537-pnav: new board port

Mike Frysinger vapier at gentoo.org
Tue Feb 10 07:21:16 CET 2009


Signed-off-by: Mike Frysinger <vapier at gentoo.org>
---
 MAINTAINERS                   |    1 +
 MAKEALL                       |    1 +
 Makefile                      |    3 +-
 board/bf537-pnav/.gitignore   |    1 +
 board/bf537-pnav/Makefile     |   59 +++++++++
 board/bf537-pnav/bf537-pnav.c |   43 +++++++
 board/bf537-pnav/config.mk    |   32 +++++
 board/bf537-pnav/nand.c       |  100 +++++++++++++++
 board/bf537-pnav/spi_flash.c  |    2 +
 board/bf537-pnav/u-boot.lds.S |  143 ++++++++++++++++++++++
 include/configs/bf537-pnav.h  |  271 +++++++++++++++++++++++++++++++++++++++++
 11 files changed, 655 insertions(+), 1 deletions(-)
 create mode 100644 board/bf537-pnav/.gitignore
 create mode 100644 board/bf537-pnav/Makefile
 create mode 100644 board/bf537-pnav/bf537-pnav.c
 create mode 100644 board/bf537-pnav/config.mk
 create mode 100644 board/bf537-pnav/nand.c
 create mode 100644 board/bf537-pnav/spi_flash.c
 create mode 100644 board/bf537-pnav/u-boot.lds.S
 create mode 100644 include/configs/bf537-pnav.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f56fccf..5a790e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ Blackfin Team <u-boot-devel at blackfin.uclinux.org>
 	BF527-EZKIT	BF527
 	BF533-EZKIT	BF533
 	BF533-STAMP	BF533
+	BF537-PNAV	BF537
 	BF537-STAMP	BF537
 	BF538F-EZKIT	BF538
 	BF548-EZKIT	BF548
diff --git a/MAKEALL b/MAKEALL
index 362730a..6fe71aa 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -785,6 +785,7 @@ LIST_blackfin="		\
 	bf527-ezkit	\
 	bf533-ezkit	\
 	bf533-stamp	\
+	bf537-pnav	\
 	bf537-stamp	\
 	bf538f-ezkit	\
 	bf548-ezkit	\
diff --git a/Makefile b/Makefile
index 8fbc58f..8c1e1f7 100644
--- a/Makefile
+++ b/Makefile
@@ -3290,7 +3290,7 @@ suzaku_config:	unconfig
 
 # Analog Devices boards
 BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
-	bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
+	bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
 
 # Bluetechnix tinyboards
 BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
@@ -3458,6 +3458,7 @@ clean:
 	       $(obj)board/{integratorap,integratorcp}/u-boot.lds	  \
 	       $(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds	  \
 	       $(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
+	       $(obj)board/bf537-pnav/u-boot.lds			  \
 	       $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf537-pnav/.gitignore b/board/bf537-pnav/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf537-pnav/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
new file mode 100644
index 0000000..e6077b4
--- /dev/null
+++ b/board/bf537-pnav/Makefile
@@ -0,0 +1,59 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_CMD_NAND)   += nand.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
new file mode 100644
index 0000000..3d6ef47
--- /dev/null
+++ b/board/bf537-pnav/bf537-pnav.c
@@ -0,0 +1,43 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: ADI BF537 PNAV board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/bf537-pnav/config.mk b/board/bf537-pnav/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/bf537-pnav/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf537-pnav/nand.c b/board/bf537-pnav/nand.c
new file mode 100644
index 0000000..181e83d
--- /dev/null
+++ b/board/bf537-pnav/nand.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <nand.h>
+
+#define CONCAT(a,b,c,d) a ## b ## c ## d
+#define PORT(a,b)  CONCAT(pPORT,a,b,)
+
+#ifndef CONFIG_NAND_GPIO_PORT
+#define CONFIG_NAND_GPIO_PORT F
+#endif
+
+/*
+ * hardware specific access to control-lines
+ */
+static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	register struct nand_chip *this = mtd->priv;
+	u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
+		else
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
+		else
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE;
+		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
+	}
+	this->IO_ADDR_R = this->IO_ADDR_W;
+
+	/* Drain the writebuffer */
+	SSYNC();
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int bfin_device_ready(struct mtd_info *mtd)
+{
+	int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
+	SSYNC();
+	return ret;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
+	*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
+	*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
+
+	nand->cmd_ctrl = bfin_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->dev_ready = bfin_device_ready;
+	nand->chip_delay = 30;
+
+	return 0;
+}
diff --git a/board/bf537-pnav/spi_flash.c b/board/bf537-pnav/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf537-pnav/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf537-pnav/u-boot.lds.S b/board/bf537-pnav/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/bf537-pnav/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+	l1_code : ORIGIN = L1_INST_SRAM,            LENGTH = L1_INST_SRAM_SIZE
+	l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+	.text :
+	{
+		cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+		/* WARNING - the following is hand-optimized to fit within
+		 * the sector before the environment sector. If it throws
+		 * an error during compilation remove an object here to get
+		 * it linked after the configuration sector.
+		 */
+
+		cpu/blackfin/traps.o		(.text .text.*)
+		cpu/blackfin/interrupt.o	(.text .text.*)
+		cpu/blackfin/serial.o		(.text .text.*)
+		common/dlmalloc.o		(.text .text.*)
+		lib_generic/crc32.o		(.text .text.*)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+		common/env_embedded.o	(.text .text.*)
+#endif
+
+		__initcode_start = .;
+		cpu/blackfin/initcode.o (.text .text.*)
+		__initcode_end = .;
+
+		*(.text .text.*)
+	} >ram
+
+	.rodata :
+	{
+		. = ALIGN(4);
+		*(.rodata .rodata.*)
+		*(.rodata1)
+		*(.eh_frame)
+		. = ALIGN(4);
+	} >ram
+
+	.data :
+	{
+		. = ALIGN(256);
+		*(.data .data.*)
+		*(.data1)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	} >ram
+
+	.u_boot_cmd :
+	{
+		___u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		___u_boot_cmd_end = .;
+	} >ram
+
+	.text_l1 :
+	{
+		. = ALIGN(4);
+		__stext_l1 = .;
+		*(.l1.text)
+		. = ALIGN(4);
+		__etext_l1 = .;
+	} >l1_code AT>ram
+	__stext_l1_lma = LOADADDR(.text_l1);
+
+	.data_l1 :
+	{
+		. = ALIGN(4);
+		__sdata_l1 = .;
+		*(.l1.data)
+		*(.l1.bss)
+		. = ALIGN(4);
+		__edata_l1 = .;
+	} >l1_data AT>ram
+	__sdata_l1_lma = LOADADDR(.data_l1);
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.sbss) *(.scommon)
+		*(.dynbss)
+		*(.bss .bss.*)
+		*(COMMON)
+		__bss_end = .;
+	} >ram
+}
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
new file mode 100644
index 0000000..6ecf15f
--- /dev/null
+++ b/include/configs/bf537-pnav.h
@@ -0,0 +1,271 @@
+/*
+ * U-boot - Configuration file for BF537 PNAV board
+ */
+
+#ifndef __CONFIG_BF537_PNAV_H__
+#define __CONFIG_BF537_PNAV_H__
+
+#include <asm/blackfin-config-pre.h>
+
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_BAUDRATE		115200
+
+#ifndef __ADSPBF534__
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_DCACHE_OFF
+#define CONFIG_ICACHE_OFF
+
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE	0
+
+#define CONFIG_RTC_BFIN		1
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz                            */
+#define CONFIG_CLKIN_HZ          24576000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
+/*                                                  1=CLKIN/2    */
+#define CONFIG_CLKIN_HALF               0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
+/*                                               1=bypass PLL    */
+#define CONFIG_PLL_BYPASS               0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
+/* Values can range from 1-64                                    */
+#define CONFIG_VCO_MULT			20
+/* CONFIG_CCLK_DIV controls what the core clock divider is       */
+/* Values can be 1, 2, 4, or 8 ONLY                              */
+#define CONFIG_CCLK_DIV			1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15                                    */
+#define CONFIG_SCLK_DIV			4
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider     */
+/* Values can range from 2-65535                                 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                  */
+#define CONFIG_SPI_BAUD                 2
+
+#define CONFIG_LOADS_ECHO	1
+
+#define CONFIG_SYS_AUTOLOAD                    "no"    /*rarpb, bootp or dhcp commands will perform only a */
+                                                /* configuration lookup from the BOOTP/DHCP server, */
+                                                /* but not try to load any image using TFTP         */
+
+/*
+ * Network Settings
+ */
+/* network support */
+#ifdef CONFIG_BFIN_MAC
+#define CONFIG_IPADDR           192.168.0.15
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_GATEWAYIP        192.168.0.1
+#define CONFIG_SERVERIP         192.168.0.2
+#define CONFIG_HOSTNAME         bf537-pnav
+#endif
+
+#define CONFIG_ROOTPATH		/romfs
+/* Uncomment next line to use fixed MAC address */
+#define CONFIG_ETHADDR          02:80:ad:24:21:18
+/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY	-1
+#else
+# define CONFIG_BOOTDELAY	5
+#endif
+
+#define CONFIG_SYS_LONGHELP			1
+#define CONFIG_BOOT_RETRY_TIME		-1	/* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND 		"run ramboot"
+
+#define CONFIG_BF537_NAND 		/* Add nand flash support */
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMI
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#ifndef CONFIG_BFIN_MAC
+#undef CONFIG_CMD_NET
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=yaffs"
+#define CONFIG_LOADADDR	0x1000000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+# define BOOT_ENV_SETTINGS \
+	"update=tftpboot $(loadaddr) u-boot.bin;" \
+		"protect off 0x20000000 0x2003FFFF;" \
+		"erase 0x20000000 0x2003FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+# define BOOT_ENV_SETTINGS \
+	"update=tftpboot $(loadaddr) u-boot.ldr;" \
+		"eeprom write $(loadaddr) 0x0 $(filesize);\0"
+#else
+# define BOOT_ENV_SETTINGS
+#endif
+#ifdef CONFIG_BFIN_MAC
+# define NETWORK_ENV_SETTINGS \
+	"nfsargs=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$(serverip):$(rootpath)\0" \
+	"addip=setenv bootargs $(bootargs) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+		":$(hostname):eth0:off\0" \
+	"ramboot=tftpboot $(loadaddr) linux;" \
+		"run ramargs;run addip;bootelf\0" \
+	"nfsboot=tftpboot $(loadaddr) linux;" \
+		"run nfsargs;run addip;bootelf\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NETWORK_ENV_SETTINGS \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
+	"flashboot=bootm 0x20100000\0" \
+	"nandboot=nand read $(loadaddr) 0x20000 0x100000;bootm $(loadaddr)" \
+	BOOT_ENV_SETTINGS
+
+#define CONFIG_SYS_PROMPT "bfin> "
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03F00000	/* 1 ... 63 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR		0x01000000	/* default load address */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_MEM_SIZE                 64             /* 128, 64, 32, 16 */
+#define CONFIG_SYS_MAX_RAM_SIZE	0x04000000
+
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0x20004000
+#define CONFIG_ENV_OFFSET	0x4000
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define ENV_IS_EMBEDDED_CUSTOM
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_ENV_OFFSET	0x4000
+#endif
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
+
+/* JFFS Partition offset set  */
+#define CONFIG_SYS_JFFS2_FIRST_BANK 0
+#define CONFIG_SYS_JFFS2_NUM_BANKS  1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR                 15
+
+
+#define FLASH_TOT_SECT		71
+
+
+/*
+ * Serial Flash Infomation
+ */
+	/* 	  NAME	    Sector Size	   Sectors
+	 *	 m25p05     32 * 1024        2
+	 *	 m25p10     32 * 1024        4
+	 *	 m25p20     64 * 1024        4
+	 *	 m25p40     64 * 1024        8
+	 *	 m25p80     64 * 1024        16
+	 *	 m25p16     64 * 1024        32
+	 *	 m25p32     64 * 1024        64
+	 *	 m25p64     64 * 1024        128
+	 *	 m25p128   256 * 1024        64
+	 */
+
+#define CONFIG_SPI
+#define CONFIG_SYS_I2C_FRAM
+
+/*
+ * Board NAND Infomation
+ */
+
+#define CONFIG_SYS_NAND_ADDR          0x20100000
+#define CONFIG_SYS_NAND_BASE          CONFIG_SYS_NAND_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE    1
+#define SECTORSIZE             512
+#define ADDR_COLUMN             1
+#define ADDR_PAGE               2
+#define ADDR_COLUMN_PAGE        3
+#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_MAX_FLOORS        1
+#define NAND_MAX_CHIPS         1
+#define BFIN_NAND_READY		PF12
+
+#define CONFIG_NAND_GPIO_PORT H
+
+#define NAND_WAIT_READY(nand)  			\
+	do { 					\
+		int timeout = 0; 		\
+		while(!(*pPORTHIO & BFIN_NAND_READY)) 	\
+			if (timeout++ > 100000)	\
+				break;		\
+	} while (0)
+
+#define BFIN_NAND_CLE          (1<<2)                  /* A2 -> Command Enable */
+#define BFIN_NAND_ALE          (1<<1)                  /* A1 -> Address Enable */
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+
+#define CONFIG_SYS_BOOTM_LEN			0x4000000       /* Large Image Length, set to 64 Meg */
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
+
+#define CONFIG_EBIU_SDRRC_VAL  0x3b7
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+#define CONFIG_EBIU_SDBCTL_VAL 0x25
+
+#define CONFIG_EBIU_AMGCTL_VAL               0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL              0x7BB033B0
+#define CONFIG_EBIU_AMBCTL1_VAL              0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
+
+#endif
-- 
1.6.1.2



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