[U-Boot] [PATCH 3/6] Poseidon Board Support
Vivek
v.dalal at samsung.com
Wed Jul 1 13:25:01 CEST 2009
Added board/poseidon directory and poseidon board specific files in it.
Signed-off-by: Vivek Dalal <v.dalal at samsung.com>
---
board/poseidon/Makefile | 48 ++++
board/poseidon/config.mk | 20 +
board/poseidon/load.S | 14 +
board/poseidon/lowlevel_init.S | 197 +++++++++++++++++
board/poseidon/mem.c | 226 ++++++++++++++++++++
board/poseidon/poseidon.c | 625 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
board/poseidon/sys_info.c | 488 +++++++++++++++++++++++++++++++++++++++++++
board/poseidon/u-boot.lds | 56 +++++
8 files changed, 1674 insertions(+)
diff --git a/board/poseidon/Makefile b/board/poseidon/Makefile
index e69de29..edbc696 100644
--- a/board/poseidon/Makefile
+++ b/board/poseidon/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2009-2010
+# Samsung Electronics, <www.samsung.com>
+# Vivek Dalal <v.dalal at samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := poseidon.o mem.o sys_info.o
+SOBJS := lowlevel_init.o load.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/poseidon/config.mk b/board/poseidon/config.mk
index e69de29..d123d2b 100644
--- a/board/poseidon/config.mk
+++ b/board/poseidon/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2004
+# Samsung Electronics, <www.samsung.com>
+# Vivek Dalal <v.dalal at samsung.com>
+#
+# Poseidon boad uses OMAP2430 (ARM1136) cpu
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x83e80000
+
+# Handy to get symbols to debug ROM version.
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0x08000000
+#TEXT_BASE = 0x04000000
diff --git a/board/poseidon/load.S b/board/poseidon/load.S
index e69de29..d38f66a 100644
--- a/board/poseidon/load.S
+++ b/board/poseidon/load.S
@@ -0,0 +1,14 @@
+.globl jumpto_addr
+.globl jumpto_addr_forsave
+jumpto_addr:
+ stmfd sp!, {r0 - r12, lr}
+ add lr, pc, #2
+ mov pc, r0
+ ldmfd sp!, {r0 - r12, pc}
+
+jumpto_addr_forsave:
+ stmfd sp!, {r0 - r12, lr}
+ mov r1, #0
+ add lr, pc, #2
+ mov pc, r0
+ ldmfd sp!, {r0 - r12, pc}
diff --git a/board/poseidon/lowlevel_init.S b/board/poseidon/lowlevel_init.S
index e69de29..ecb8230 100644
--- a/board/poseidon/lowlevel_init.S
+++ b/board/poseidon/lowlevel_init.S
@@ -0,0 +1,197 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2009-2010
+ * Samsung Electronics, <www.samsung.com>
+ * Vivek Dalal <v.dalal at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap24xx.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/*****************************************************************************
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ * R2 = dpll value
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ sub sp, sp, #0x4 /* get some stack space */
+ str r4, [sp] /* save r4's value */
+
+ /* move into fast relock bypass */
+ ldr r8, pll_ctl_add
+ mov r4, #0x2
+ str r4, [r8]
+ ldr r4, pll_stat
+block:
+ ldr r8, [r4] /* wait for bypass to take effect */
+ and r8, r8, #0x3
+ cmp r8, #0x1
+ bne block
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r4, pll_div_add
+ ldr r8, pll_div_val
+ str r8, [r4]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r4, flash_cfg3_addr
+ ldr r8, flash_cfg3_val
+ str r8, [r4]
+ ldr r4, flash_cfg4_addr
+ ldr r8, flash_cfg4_val
+ str r8, [r4]
+ ldr r4, flash_cfg5_addr
+ ldr r8, flash_cfg5_val
+ str r8, [r4]
+ ldr r4, flash_cfg1_addr
+ ldr r8, [r4]
+ orr r8, r8, #0x3 /* up gpmc divider */
+ str r8, [r4]
+
+ /* setup to 2x loop though code. The first loop pre-loads the
+ * icache, the 2nd commits the prcm config, and locks the dpll
+ */
+ mov r4, #0x1000 /* spin spin spin */
+ mov r8, #0x4 /* first pass condition & set registers */
+ cmp r8, #0x4
+2:
+ ldrne r8, [r3] /* DPLL lock check */
+ and r8, r8, #0x7
+ cmp r8, #0x2
+ beq 4f
+3:
+ subeq r8, r8, #0x1
+ streq r8, [r0] /* commit dividers (2nd time) */
+ nop
+lloop1:
+ sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop1
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ streq r2, [r1] /* lock dpll (2nd time) */
+ nop
+lloop2:
+ sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop2
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ ldreq r8, [r3] /* get lock condition for dpll */
+ cmp r8, #0x4 /* first time though? */
+ bne 2b
+ moveq r8, #0x2 /* set to dpll check condition. */
+ beq 3b /* if condition not true branch */
+4:
+ ldr r4, [sp]
+ add sp, sp, #0x4 /* return stack space */
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_stat:
+ .word CM_IDLEST_CKGEN
+pll_div_add:
+ .word CM_CLKSEL1_PLL
+pll_div_val:
+ .word DPLL_VAL /* DPLL setting (300MHz default) */
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* map interrupt controller */
+ ldr r0, VAL_INTH_SETUP
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+VAL_INTH_SETUP:
+ .word PERIFERAL_PORT_BASE
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
diff --git a/board/poseidon/mem.c b/board/poseidon/mem.c
index e69de29..c30d77e 100644
--- a/board/poseidon/mem.c
+++ b/board/poseidon/mem.c
@@ -0,0 +1,226 @@
+/*
+ *(C) Copyright 2009-2010
+ * Samsung Electronics, <www.samsung.com>
+ * Vivek Dalal <v.dalal at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or(at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap24xx.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <environment.h>
+#include <command.h>
+
+/****** DATA STRUCTURES ************/
+
+/* Only One NAND allowed on board at a time.
+* The GPMC CS Base for the same
+*/
+
+/* Board CS Organization - Poseidon */
+static const unsigned char chip_sel_sdp[][GPMC_MAX_CS] = {
+ /* GPMC CS Indices */
+ /* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0},
+ /* 7 ON ON ON */
+ {PROC_ONENAND, PROC_NAND, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1},
+};
+
+
+/* Values for each of the chips */
+static u32 gpmc_mpdb[GPMC_MAX_REG] = {
+ MPDB_GPMC_CONFIG1,
+ MPDB_GPMC_CONFIG2,
+ MPDB_GPMC_CONFIG3,
+ MPDB_GPMC_CONFIG4,
+ MPDB_GPMC_CONFIG5,
+ MPDB_GPMC_CONFIG6, 0
+};
+static u32 gpmc_onenand[GPMC_MAX_REG] = {
+ ONENAND_GPMC_CONFIG1,
+ ONENAND_GPMC_CONFIG2,
+ ONENAND_GPMC_CONFIG3,
+ ONENAND_GPMC_CONFIG4,
+ ONENAND_GPMC_CONFIG5,
+ ONENAND_GPMC_CONFIG6, 0
+};
+
+
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in 12MHz bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile("1 : \n" "subs %0, %1, #1\n"
+ "bne 1b" : "=r"(loops) : "0"(loops));
+}
+
+/**********************************************************************
+ * prcm_init() - inits clocks for PRCM.
+ * -- called from SRAM, or Flash(using temp SRAM stack).
+ **********************************************************************/
+void prcm_init(void)
+{
+}
+
+/***********************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ * command line mem=xyz use all memory with out discontigious support
+ * compiled in. Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ ***********************************************************************/
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(SDRC_CS0_OSET);
+ size /= SZ_32M; /* find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ * mem_ok() - test used to see if timings are correct
+ * for a part. Helps in gussing which part
+ * we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+ u32 val1, val2, addr;
+ u32 pattern = 0x12345678;
+
+ addr = OMAP24XX_SDRC_CS0;
+
+ __raw_writel(0x0, addr + 0x400); /* clear pos A */
+ __raw_writel(pattern, addr); /* pattern to pos B */
+ __raw_writel(0x0, addr + 4); /* remove pattern off the bus */
+ val1 = __raw_readl(addr + 0x400); /* get pos A value */
+ val2 = __raw_readl(addr); /* get val2 */
+
+ if ((val1 != 0) || (val2 != pattern)) { /* see if pos A value changed */
+ return 0;
+ } else
+ return 1;
+}
+
+/********************************************************
+ * sdrc_init() - init the sdrc chip selects CS0 and CS1
+ * - early init routines, called from flash or
+ * SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+#define EARLY_INIT 1
+ /* only init up first bank here */
+ do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
+}
+
+/******************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *****************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+ /* Done in ONENAND IPL */
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode(SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+
+ u32 mux = 0, mtype, mwidth, gpmc_base = 0;
+ u32 size = 0x0;
+ u32 base = 0x0;
+ unsigned char *config_sel = NULL;
+
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */
+
+ /* discover bus connection from sysboot */
+ mux = BIT9;
+ mtype = 0x7;
+
+ mwidth = WIDTH_16BIT;
+
+ /* setup cs0 */
+ __raw_writel(0, GPMC_CONFIG7_0); /* disable current map */
+ sdelay(1000);
+ /* GPMC5 is always MPDB.. need to know the chip info */
+ gpmc_base = GPMC_CONFIG_CS0 + (5 * GPMC_CONFIG_WIDTH);
+ gpmc_mpdb[0] |= mux;
+ base = DEBUG_BASE;
+ size = DBG_MPDB_SIZE;
+
+ __raw_writel(0, GPMC_CONFIG7 + gpmc_base);
+ sdelay(1000);
+ /* Delay for settling */
+ __raw_writel(gpmc_mpdb[0], GPMC_CONFIG1 + gpmc_base);
+ __raw_writel(gpmc_mpdb[1], GPMC_CONFIG2 + gpmc_base);
+ __raw_writel(gpmc_mpdb[2], GPMC_CONFIG3 + gpmc_base);
+ __raw_writel(gpmc_mpdb[3], GPMC_CONFIG4 + gpmc_base);
+ __raw_writel(gpmc_mpdb[4], GPMC_CONFIG5 + gpmc_base);
+ __raw_writel(gpmc_mpdb[5], GPMC_CONFIG6 + gpmc_base);
+ /* Enable the config */
+
+ __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), GPMC_CONFIG7 + gpmc_base);
+
+ sdelay(2000);
+ config_sel = (unsigned char *)(chip_sel_sdp[mtype]);
+ gpmc_base = GPMC_CONFIG_CS0 + (0 * GPMC_CONFIG_WIDTH);
+ base = 0x0;
+ size = PROC_ONENAND_SIZE;
+ __raw_writel(0, GPMC_CONFIG7 + gpmc_base);
+ sdelay(1000);
+ /* Delay for settling */
+ __raw_writel(gpmc_onenand[0], GPMC_CONFIG1 + gpmc_base);
+ __raw_writel(gpmc_onenand[1], GPMC_CONFIG2 + gpmc_base);
+ __raw_writel(gpmc_onenand[2], GPMC_CONFIG3 + gpmc_base);
+ __raw_writel(gpmc_onenand[3], GPMC_CONFIG4 + gpmc_base);
+ __raw_writel(gpmc_onenand[4], GPMC_CONFIG5 + gpmc_base);
+ __raw_writel(gpmc_onenand[5], GPMC_CONFIG6 + gpmc_base);
+ /* Enable the config */
+
+ __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), GPMC_CONFIG7 + gpmc_base);
+
+ sdelay(2000);
+
+}
diff --git a/board/poseidon/poseidon.c b/board/poseidon/poseidon.c
index e69de29..3f2d4b1 100644
--- a/board/poseidon/poseidon.c
+++ b/board/poseidon/poseidon.c
@@ -0,0 +1,617 @@
+/*
+ *(C) Copyright 2009-2010
+ * Samsung Electronics, <www.samsung.com>
+ * Vivek Dalal <v.dalal at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or(at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap24xx.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#ifdef CONFIG_CMD_NAND
+#include <linux/mtd/nand_legacy.h>
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
+#define write_config_reg(reg, value) \
+do { \
+ writeb(value, reg); \
+} while (0)
+
+#define mask_config_reg(reg, mask) \
+do { \
+ char value = readb(reg) & ~(mask); \
+ writeb(value, reg); \
+} while (0)
+
+void wait_for_command_complete(unsigned int wd_base);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile("1 : \n" "subs %0, %1, #1\n"
+ "bne 1b" : "=r"(loops) : "0"(loops));
+}
+
+void muxSetupUART1(void)
+{
+ /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
+ /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
+ /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
+ /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
+
+}
+
+
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRM, finish GPMC */
+
+ (*(volatile unsigned int*)0x49002030) |= (0x18<<16);
+ *(volatile unsigned int*)0x49006200 |= (1<<17);
+ *(volatile unsigned int*)0x49006210 |= (1<<17);
+ *(volatile unsigned int*)0x490062A0 |= (1<<17);
+ __raw_writeb(0x1b, 0x4900211a);
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP_POSEIDON;
+ /*add of boot parameters*/
+ gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100);
+
+ return 0;
+
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ *(GP Device only)
+ *****************************************/
+void secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1 0xFFFFFFFF
+#define UNLOCK_2 0x00000000
+#define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE(PM_RT)*/
+ /* REQ_INFO_PERMISSION_1 L*/
+ __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68);
+ /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50);
+ /* WRITE_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58);
+ /* ADDR_MATCH_1 L*/
+ __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60);
+ /* REQ_INFO_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48);
+ /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50);
+ /* WRITE_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58);
+ /* REQ_INFO_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48);
+ /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50);
+ /* WRITE_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58);
+ /* ADDR_MATCH_2 L*/
+ __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80);
+
+ /* IVA Changes */
+ /* REQ_INFO_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48);
+ /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50);
+ /* WRITE_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58);
+
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+
+void try_unlock_sram(void)
+{
+ int mode;
+
+ /* if GP device unlock device SRAM for general use */
+ /* secure code breaks for Secure/Emulation device-HS/E/T*/
+ mode = get_device_type();
+ if (mode == GP_DEVICE)
+ secure_unlock();
+ return;
+
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with sram stack.
+ **********************************************************/
+void s_init(void)
+{
+ int in_sdram = running_in_sdram();
+ /* u32 rev = get_cpu_rev(); unused as of now.. */
+
+ watchdog_init();
+ try_unlock_sram();/* Do SRAM availability first*/
+
+ set_muxconf_regs();
+ delay(100);
+
+ if (!in_sdram)
+ prcm_init();
+
+ peripheral_enable();
+ icache_enable();
+ if (!in_sdram)
+ sdrc_init();
+
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet(done here so udelay works)
+ ********************************************************/
+int misc_init_r(void)
+{
+ ether_init(); /* better done here so timers are init'ed */
+ return 0;
+
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+ /* There are 4 watch dogs. 1 secure, and 3 general purpose.
+ * The ROM takes care of the secure one. Of the 3 GP ones,
+ * 1 can reset us directly, the other 2 only generate MPU interrupts
+ */
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+
+}
+
+/*******************************************************************
+ * Routine:ether_init
+ * Description: take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete.
+ ******************************************************************/
+void ether_init(void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+ int cnt = 20;
+
+ /* u32 rev = get_cpu_rev(); unused as of now */
+ __raw_writew(0x0, LAN_RESET_REGISTER);
+ do {
+ __raw_writew(0x1, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto h4reset_err_out;
+ --cnt;
+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+ cnt = 20;
+
+ do {
+ __raw_writew(0x0, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto h4reset_err_out;
+ --cnt;
+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+ udelay(1000);
+
+ *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;
+ udelay(1000);
+
+h4reset_err_out:
+ return;
+#endif
+
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int size0 = 0, size1 = 0;
+ u32 mtype, btype;
+#ifdef CONFIG_DRIVER_OMAP24XX_I2C
+ u8 data;
+#endif
+#define NOT_EARLY 0
+
+#ifdef CONFIG_DRIVER_OMAP24XX_I2C
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ select_bus(1, CONFIG_SYS_I2C_SPEED); /* select bus with T2 on it */
+#endif
+ mtype = get_mem_type();
+ display_board_info(btype);
+
+ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED))
+ /* init other chip select and map CS1 right after CS0 */
+ do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
+
+ size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+ size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = size0;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
+ gd->bd->bi_dram[1].size = size1;
+
+ return 0;
+
+}
+
+#define MUX_VAL(OFFSET,VALUE)\
+ __raw_writeb((VALUE), OMAP24XX_CTRL_BASE + (OFFSET));
+
+#ifdef CONFIG_2430
+#define MUX_DEFAULT()\
+/* SDRC */\
+MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */\
+MUX_VAL(0x0055, 0x00) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */\
+MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */\
+MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */\
+MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */\
+/* GPMC */\
+MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */\
+MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */\
+MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */\
+MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */\
+MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */\
+MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */\
+MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */\
+MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */\
+MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */\
+MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */\
+MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */\
+MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */\
+/* GPMC mux for NAND access */\
+MUX_VAL(0x0086, 0x18) /* gpmc_a9 - EN, HI, 0*/\
+MUX_VAL(0x0087, 0x18) /* gpmc_a8 - EN, HI, 0*/\
+MUX_VAL(0x0088, 0x18) /* gpmc_a7 - EN, HI, 0*/\
+MUX_VAL(0x0089, 0x18) /* gpmc_a6 - EN, HI, 0*/\
+MUX_VAL(0x008A, 0x18) /* gpmc_a5 - EN, HI, 0*/\
+MUX_VAL(0x008B, 0x18) /* gpmc_a4 - EN, HI, 0*/\
+MUX_VAL(0x008C, 0x18) /* gpmc_a3 - EN, HI, 0*/\
+MUX_VAL(0x008D, 0x18) /* gpmc_a2 - EN, HI, 0*/\
+MUX_VAL(0x008E, 0x18) /* gpmc_a1 - EN, HI, 0*/\
+MUX_VAL(0x008F, 0x18) /* gpmc_d15 - EN,HI, 0*/\
+MUX_VAL(0x0090, 0x18) /* gpmc_d14 - EN, HI, 0*/\
+MUX_VAL(0x0091, 0x18) /* gpmc_d13 - EN, HI, 0*/\
+MUX_VAL(0x0092, 0x18) /* gpmc_d12 - EN, HI, 0*/\
+MUX_VAL(0x0093, 0x18) /* gpmc_d11 - EN, HI, 0*/\
+MUX_VAL(0x0094, 0x18) /* gpmc_d10 - EN, HI, 0*/\
+MUX_VAL(0x0095, 0x18) /* gpmc_d9 - EN, HI, 0 */\
+MUX_VAL(0x0096, 0x18) /* gpmc_d8 - EN, HI, 0*/\
+/* DSS */\
+MUX_VAL(0x009F, 0x00) /* dss_data0- Dis, 0 */\
+MUX_VAL(0x00A0, 0x00) /* dss_data1- Dis, 0 */\
+MUX_VAL(0x00A1, 0x00) /* dss_data2- Dis, 0 */\
+MUX_VAL(0x00A2, 0x00) /* dss_data3- Dis, 0 */\
+MUX_VAL(0x00A3, 0x00) /* dss_data4- Dis, 0 */\
+MUX_VAL(0x00A4, 0x00) /* dss_data5- Dis, 0 */\
+MUX_VAL(0x00A5, 0x00) /* dss_data6- Dis, 0 */\
+MUX_VAL(0x00A6, 0x00) /* dss_data7- Dis, 0 */\
+MUX_VAL(0x00A7, 0x00) /* dss_data8- Dis, 0 */\
+MUX_VAL(0x00A8, 0x00) /* dss_data9- Dis, 0 */\
+MUX_VAL(0x00A9, 0x00) /* dss_data10- Dis, 0 */\
+MUX_VAL(0x00AA, 0x00) /* dss_data11- Dis, 0 */\
+MUX_VAL(0x00AB, 0x00) /* dss_data12- Dis, 0 */\
+MUX_VAL(0x00AC, 0x00) /* dss_data13- Dis, 0 */\
+MUX_VAL(0x00AD, 0x00) /* dss_data14- Dis, 0 */\
+MUX_VAL(0x00AE, 0x00) /* dss_data15- Dis, 0 */\
+MUX_VAL(0x00AF, 0x00) /* dss_data16- Dis, 0 */\
+MUX_VAL(0x00B0, 0x00) /* dss_data17- Dis, 0 */\
+MUX_VAL(0x00B9, 0x00) /* dss_hsync- Dis, 0 */\
+MUX_VAL(0x00BA, 0x00) /* dss_acbias- Dis, 0 */\
+MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */\
+MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */\
+MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */\
+MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */\
+MUX_VAL(0x00B5, 0x1B) /* mcbsp2_dr- EN, HI, 3, ->gpio_11 */\
+MUX_VAL(0x00B6, 0x1B) /* mcbsp2_clkx- EN, HI, 3, ->gpio_12 */\
+MUX_VAL(0x00B7, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\
+MUX_VAL(0x00B8, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\
+MUX_VAL(0x00B9, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\
+MUX_VAL(0x00BA, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\
+/* CONTROL */\
+MUX_VAL(0x00BB, 0x00) /* sys_nrespwron- Dis, 0 */\
+MUX_VAL(0x00BC, 0x00) /* sys_nreswarm- Dis, 0 */\
+MUX_VAL(0x00BD, 0x18) /* sys_nirq0- EN, HI, 0 */\
+/*MUX_VAL(0x00BD, 0x1B)*/ /* sys_nirq0- EN, HI, 3, ->gpio_56 */\
+MUX_VAL(0x00BE, 0x18) /* sys_nirq1- EN, HI, 0 */\
+MUX_VAL(0x00C7, 0x00) /* gpio_132- Dis, 0, ->gpio132 */\
+MUX_VAL(0x00CB, 0x00) /* gpio_133- Dis, 0, ->gpio133 */\
+MUX_VAL(0x00C9, 0x18) /* sys_clkout- Dis, 0 */\
+/*MUX_VAL(0x00C9, 0x1B)*/ /* sys_clkout- EN, HI, 3, ->gpio_111 */\
+MUX_VAL(0x00CC, 0x18) /* jtag_emu1- EN, HI, 0 */\
+MUX_VAL(0x00CD, 0x18) /* jtag_emu0- EN, HI, 0 */\
+/* CAMERA */\
+MUX_VAL(0x00DD, 0x02) /* cam_d0- Dis, 2, sti_dout */\
+MUX_VAL(0x00DC, 0x02) /* cam_d1- Dis, 2, sti_din */\
+MUX_VAL(0x00DB, 0x1B) /* cam_d2- EN, HI, 3, ->gpio_129 */\
+MUX_VAL(0x00DA, 0x1B) /* cam_d3- EN, HI, 3, ->gpio_128 */\
+MUX_VAL(0x00D9, 0x00) /* cam_d4- Dis, 0 */\
+MUX_VAL(0x00D8, 0x00) /* cam_d5- Dis, 0 */\
+MUX_VAL(0x00D7, 0x00) /* cam_d6- Dis, 0 */\
+MUX_VAL(0x00D6, 0x00) /* cam_d7- Dis, 0 */\
+MUX_VAL(0x00D5, 0x00) /* cam_d8- Dis, 0 */\
+MUX_VAL(0x00D4, 0x00) /* cam_d9- Dis, 0 */\
+MUX_VAL(0x00E3, 0x00) /* cam_d10- Dis, 0 */\
+MUX_VAL(0x00E2, 0x00) /* cam_d11- Dis, 0 */\
+MUX_VAL(0x00DE, 0x00) /* cam_hs- Dis, 0 */\
+MUX_VAL(0x00DF, 0x00) /* cam_vs- Dis, 0 */\
+MUX_VAL(0x00E0, 0x00) /* cam_lclk- Dis, 0 */\
+MUX_VAL(0x00E1, 0x00) /* cam_xclk- Dis, 0 */\
+MUX_VAL(0x00E4, 0x01) /* gpio_134- Dis, 1, ->ccp_datn */\
+MUX_VAL(0x00E5, 0x01) /* gpio_135- Dis, 1, ->ccp_datp */\
+MUX_VAL(0x00E6, 0x01) /* gpio_136- Dis, 1, ->ccp_clkn */\
+MUX_VAL(0x00E7, 0x01) /* gpio_137- Dis, 1, ->ccp_clkp */\
+MUX_VAL(0x00E8, 0x01) /* gpio_138- Dis, 1, ->spi3_clk */\
+MUX_VAL(0x00E9, 0x01) /* gpio_139- Dis, 1, ->spi3_cs0 */\
+MUX_VAL(0x00EA, 0x01) /* gpio_140- Dis, 1, ->spi3_simo */\
+MUX_VAL(0x00EB, 0x01) /* gpio_141- Dis, 1, ->spi3_somi */\
+MUX_VAL(0x00EC, 0x18) /* gpio_142- EN, HI, 0, ->gpio_142 */\
+MUX_VAL(0x00ED, 0x18) /* gpio_154- EN, HI, 0, ->gpio_154 */\
+MUX_VAL(0x00EE, 0x18) /* gpio_148- EN, HI, 0, ->gpio_148 */\
+MUX_VAL(0x00EF, 0x18) /* gpio_149- EN, HI, 0, ->gpio_149 */\
+MUX_VAL(0x00F0, 0x18) /* gpio_150- EN, HI, 0, ->gpio_150 */\
+MUX_VAL(0x00F1, 0x18) /* gpio_152- EN, HI, 0, ->gpio_152 */\
+MUX_VAL(0x00F2, 0x18) /* gpio_153- EN, HI, 0, ->gpio_153 */\
+/* MMC1 */\
+MUX_VAL(0x00F3, 0x00) /* mmc1_clko- Dis, 0 */\
+MUX_VAL(0x00F4, 0x18) /* mmc1_cmd- EN, HI, 0 */\
+MUX_VAL(0x00F5, 0x18) /* mmc1_dat0- EN, HI, 0 */\
+MUX_VAL(0x00F6, 0x18) /* mmc1_dat1- EN, HI, 0 */\
+MUX_VAL(0x00F7, 0x18) /* mmc1_dat2- EN, HI, 0 */\
+MUX_VAL(0x00F8, 0x18) /* mmc1_dat3- EN, HI, 0 */\
+/* MMC2 */\
+MUX_VAL(0x00F9, 0x00) /* mmc2_clko- Dis, 0 */\
+MUX_VAL(0x00FA, 0x18) /* mmc2_cmd- EN, HI, 0 */\
+MUX_VAL(0x00FB, 0x18) /* mmc2_dat0- EN, HI, 0 */\
+MUX_VAL(0x00FC, 0x18) /* mmc2_dat1- EN, HI, 0 */\
+MUX_VAL(0x00FD, 0x18) /* mmc2_dat2- EN, HI, 0 */\
+MUX_VAL(0x00FE, 0x18) /* mmc2_dat3- EN, HI, 0 */\
+/* UART2 */\
+MUX_VAL(0x00FF, 0x00) /* uart2_cts- Dis, 0 */\
+MUX_VAL(0x0100, 0x1B) /* uart2_rts- Dis, 0 gpio-68 by jhchoi*/\
+MUX_VAL(0x0101, 0x00) /* uart2_tx- Dis, 0 */\
+MUX_VAL(0x0102, 0x1B) /* uart2_rx- Dis, 0 */\
+/* MCBSP3 */\
+MUX_VAL(0x0103, 0x00) /* mcbsp3_clkx- Dis, 0 */\
+MUX_VAL(0x0104, 0x00) /* mcbsp3_fsx- Dis, 0 */\
+MUX_VAL(0x0105, 0x00) /* mcbsp3_dr- Dis, 0 */\
+MUX_VAL(0x0106, 0x00) /* mcbsp3_dx- Dis, 0 */\
+/* SSI1 */\
+MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */\
+MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */\
+MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */\
+MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */\
+MUX_VAL(0x010B, 0x01) /* gpio_63- Dis, 1, ->mcbsp4_clkx */\
+MUX_VAL(0x010C, 0x01) /* ssi1_flag_rx- Dis, 1, ->mcbsp4_dr */\
+MUX_VAL(0x010D, 0x01) /* ssi1_rdy_rx- Dis, 1, ->mcbsp4_dx */\
+MUX_VAL(0x010E, 0x01) /* ssi1_wake- Dis, 1, ->mcbsp4_fsx */\
+/* SPI1 */\
+MUX_VAL(0x010F, 0x00) /* spi1_clk- Dis, 0 */\
+MUX_VAL(0x0110, 0x00) /* spi1_simo- Dis, 0 */\
+MUX_VAL(0x0111, 0x00) /* spi1_somi- Dis, 0 */\
+MUX_VAL(0x0112, 0x00) /* spi1_cs0- Dis, 0 */\
+MUX_VAL(0x0113, 0x00) /* spi1_cs1- Dis, 0 */\
+MUX_VAL(0x0114, 0x00) /* spi1_cs2- Dis, 0 */\
+MUX_VAL(0x0115, 0x00) /* spi1_cs3- Dis, 0 */\
+/* SPI2 */\
+MUX_VAL(0x0116, 0x1B) /* spi2_clk- EN, HI, 3, ->gpio_88 */\
+MUX_VAL(0x0117, 0x1B) /* spi2_simo- EN, HI, 3, ->gpio_89 */\
+MUX_VAL(0x0118, 0x1B) /* spi2_somi- EN, HI, 3, ->gpio_90 */\
+MUX_VAL(0x0119, 0x1B) /* spi2_cs0- EN, HI, 3, ->gpio_91 */\
+/* MCBSP1 */\
+MUX_VAL(0x011A, 0x00) /* mcbsp1_clkr- Dis, 0 */\
+MUX_VAL(0x011B, 0x00) /* mcbsp1_fsr- Dis, 0 */\
+MUX_VAL(0x011C, 0x00) /* mcbsp1_dx- Dis, 0 */\
+MUX_VAL(0x011D, 0x0B) /* mcbsp1_dr- Dis, 0 */\
+MUX_VAL(0x011E, 0x00) /* mcbsp1_clks- Dis, 0 */\
+MUX_VAL(0x011F, 0x00) /* mcbsp1_fsx- Dis, 0 */\
+MUX_VAL(0x0120, 0x00) /* mcbsp1_clkx- Dis, 0 */\
+/* HDQ */\
+MUX_VAL(0x0125, 0x00) /* hdq_sio- Dis, 0 */\
+/* UART3 */\
+MUX_VAL(0x0126, 0x00) /* uart3_cts_rctx- Dis, 0 */\
+MUX_VAL(0x0127, 0x00) /* uart3_rts_sd- Dis, 0 */\
+MUX_VAL(0x0128, 0x00) /* uart3_tx_irtx- Dis, 0 */\
+MUX_VAL(0x0129, 0x00) /* uart3_rx_irrx- Dis, 0 */\
+/* OTHERS */\
+MUX_VAL(0x012B, 0x1B) /* gpio_78- EN, HI, 3, ->gpio_78 */\
+MUX_VAL(0x012C, 0x01) /* gpio_79- Dis, 1, ->secure_indicator */\
+MUX_VAL(0x012D, 0x1B) /* gpio_80- EN, HI, 3, ->gpio_80 */\
+/* MCBSP2 */\
+MUX_VAL(0x012E, 0x01) /* gpio_113- Dis, 1, ->mcbsp2_clkx */\
+MUX_VAL(0x012F, 0x01) /* gpio_114- Dis, 1, ->mcbsp2_fsx */\
+MUX_VAL(0x0130, 0x01) /* gpio_115- Dis, 1, ->mcbsp2_dr */\
+MUX_VAL(0x0131, 0x01) /* gpio_116- Dis, 1, ->mcbsp2_dx */\
+/* GPIO7-AUDIOENVDD */\
+MUX_VAL(0x012A, 0x18) /* gpio_7- EN, HI, 3, ->gpio_7 */\
+
+#else
+/* For all other platforms */
+#define MUX_DEFAULT()\
+ /* SDRC */\
+MUX_VAL(0x0054, 0x08) /* sdrc_a14 - EN, LO, 0 */\
+MUX_VAL(0x0055, 0x08) /* sdrc_a13 - EN, LO, 0 */\
+MUX_VAL(0x0056, 0x08) /* sdrc_a12 - EN, LO, 0 */\
+MUX_VAL(0x0045, 0x18) /* sdrc_ncs1 - EN, HI, 0 */\
+MUX_VAL(0x0046, 0x18) /* sdrc_ncs2 - EN, HI, 0 */\
+/* GPMC */\
+MUX_VAL(0x0030, 0x08) /* gpmc_clk - EN, LO, 0 */\
+MUX_VAL(0x0032, 0x18) /* gpmc_ncs1- EN, HI, 0 */\
+MUX_VAL(0x0033, 0x18) /* gpmc_ncs2- EN, HI, 0 */\
+MUX_VAL(0x0034, 0x18) /* gpmc_ncs3- EN, HI, 0 */\
+/* UART1 */\
+MUX_VAL(0x00B1, 0x18) /* uart1_cts- EN, HI, 0 */\
+MUX_VAL(0x00B2, 0x18) /* uart1_rts- EN, HI, 0 */\
+MUX_VAL(0x00B3, 0x18) /* uart1_tx- EN, HI, 0 */\
+MUX_VAL(0x00B4, 0x18) /* uart1_rx- EN, HI, 0 */\
+/* UART2 */\
+MUX_VAL(0x00FF, 0x18) /* uart2_cts- EN, HI, 0 */\
+MUX_VAL(0x0100, 0x18) /* uart2_rts- EN, HI, 0 */\
+MUX_VAL(0x0101, 0x18) /* uart2_tx- EN, HI, 0 */\
+MUX_VAL(0x0102, 0x18) /* uart2_rx- EN, HI, 0 */\
+/* UART3 */\
+MUX_VAL(0x0126, 0x18) /* uart3_cts_rctx- EN, HI, 0 */\
+MUX_VAL(0x0127, 0x18) /* uart3_rts_sd- EN, HI, 0 */\
+MUX_VAL(0x0127, 0x18) /* uart3_tx_irtx- EN, HI, 0 */\
+MUX_VAL(0x0127, 0x18) /* uart3_rx_irrx- EN, HI, 0 */\
+/* I2C1 */\
+MUX_VAL(0x0111, 0x00) /* i2c1_scl - DIS, NA, 0 */\
+MUX_VAL(0x0112, 0x00) /* i2c1_sda - DIS, NA, 0 */\
+
+#endif /* End of Mux Mapping */
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need
+ * to be moved from protect to primary mode.
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+ u32 cpu;
+ cpu = get_cpu_type();
+ /*Incase we have to handle multiple processors such as 2430 and 2430C */
+ if (cpu == CPU_2430) {
+ MUX_DEFAULT();
+ } else
+ return;
+
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs(GPT2, UART1,...)
+ ******************************************************************/
+void peripheral_enable(void)
+{
+ unsigned int v, if_clks1 = 0, func_clks1 = 0;
+ unsigned int if_clks2 = 0, func_clks2 = 0;
+ /* ALERT STATUS 10000 */
+ /* Enable GP2 timer. */
+ if_clks1 |= BIT4;
+ func_clks1 |= BIT4;
+ v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;/* Sys_clk input OMAP24XX_GPT2 */
+ __raw_writel(v, CM_CLKSEL2_CORE);
+ __raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CONFIG_SYS_NS16550
+ /* Enable UART1 clock */
+ func_clks1 |= BIT21;
+ if_clks1 |= BIT21;
+#endif
+#ifdef CONFIG_DRIVER_OMAP24XX_I2C
+ /* 2430 requires only the hs clock */
+ func_clks2 |= BIT20|BIT19; /* i2c1 and 2 96 meg clock input */
+ if_clks1 |= BIT20|BIT19;
+#endif
+
+ v = __raw_readl(CM_ICLKEN1_CORE) | if_clks1;/* Interface clocks on */
+ __raw_writel(v, CM_ICLKEN1_CORE);
+ v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2;/* Interface clocks on */
+ __raw_writel(v, CM_ICLKEN2_CORE);
+ v = __raw_readl(CM_FCLKEN1_CORE) | func_clks1;/* Functional Clocks on */
+ __raw_writel(v, CM_FCLKEN1_CORE);
+ v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2;/* Functional Clocks on */
+ __raw_writel(v, CM_FCLKEN2_CORE);
+ delay(1000);
+}
+
+/*****************************************************************************
+ * Routine: update_mux()
+ * Description: Update balls which are different beween boards. All should be
+ * updated to match functionaly. However, I'm only updating ones
+ * which I'll be using for now. When power comes into play they
+ * all need updating.
+ *****************************************************************************/
+void update_mux(u32 btype, u32 mtype)
+{
+ /* NOTHING as of now... */
+}
+
+#ifdef CONFIG_CMD_NAND
+void nand_init(void)
+{
+ extern flash_info_t flash_info[];
+
+ nand_probe(CONFIG_SYS_NAND_ADDR);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
+ print_size(nand_dev_desc[0].totlen, "\n");
+#ifdef CONFIG_SYS_JFFS2_MEM_NAND
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
+ /* only read kernel single meg partition */
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2;
+ /* 1024 blocks in 16meg chip(use less for raw/copied partition) */
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024;
+ /* ?, ram for now, open question, copy to RAM or adapt for NAND */
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000;
+#endif
+}
+#endif
diff --git a/board/poseidon/sys_info.c b/board/poseidon/sys_info.c
index e69de29..c64f442 100644
--- a/board/poseidon/sys_info.c
+++ b/board/poseidon/sys_info.c
@@ -0,0 +1,380 @@
+/*
+ *(C) Copyright 2009-2010
+ * Samsung Electronics, <www.samsung.com>
+ * Vivek Dalal <v.dalal at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or(at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap24xx.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h> /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/****************************************************************************
+ * check_fpga_revision number: the rev number should be a or b 0xA203/5
+ * variant did not have it, but the B101 variant has EEPROM update facility
+ ***************************************************************************/
+static inline u16 check_fpga_rev(void)
+{
+ return __raw_readw(FPGA_REV_REGISTER);
+}
+
+/****************************************************************************
+ * check_eeprom_avail: Check FPGA Availability
+ * OnBoard DEBUG FPGA registers need to be ready for us to proceed
+ * Required to retrieve the bootmode also.
+ ***************************************************************************/
+int check_eeprom_avail(u32 offset)
+{
+ return 0;
+}
+
+/**************************************************************************
+ * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch
+ * settings
+ * 1 is on
+ * 0 is off
+ * Will return Index of type of gpmc
+ ***************************************************************************/
+u32 get_gpmc0_type(void)
+{
+ u8 cs;
+ if (!check_fpga_rev())
+ /* we dont have an DEBUG FPGA??? */
+ /* Depend on #defines!! default to strata boot return param */
+ return 0x0;
+ cs = (u8) __raw_readw(DIP_SWITCH_INPUT_REG2);
+ /* The bits are inverted- S8 0-2 define the CS0 select */
+ return (~cs) & 0x07;
+}
+
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ * (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+ u32 v;
+ v = __raw_readl(TAP_IDCODE_REG);
+ v &= CPU_24XX_ID_MASK;
+
+ if (v == CPU_2430_CHIPID) {
+ return CPU_2430;
+ } else
+ return -1; /* don't know,return invalid val */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 v;
+ v = __raw_readl(TAP_IDCODE_REG);
+ v = v >> 28;
+ return v + 1;
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+ volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
+ if (*burst == H4_2420_SDRC_MR_0_SDR)
+ return 1;
+ return 0;
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+ return DDR_DISCRETE;
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+ u32 size;
+ /* get ram size field */
+ size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size *= SZ_2M; /* find size in MB */
+ return size;
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings(dip switch on h4)
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+ return 0x00000FFF & __raw_readl(CONTROL_STATUS);
+}
+
+/***************************************************************************
+ * get_gpmc0_base() - Return current address hardware will be
+ * fetching from. The below effectively gives what is correct, its a bit
+ * mis-leading compared to the TRM. For the most general case the mask
+ * needs to be also taken into account this does work in practice.
+ * - for u-boot we currently map:
+ * -- 0 to nothing,
+ * -- 4 to flash
+ * -- 8 to enent
+ * -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+ u32 b;
+
+ b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7);
+ b &= 0x1F; /* keep base [5:0] */
+ b = b << 24; /* ret 0x0b000000 */
+ return b;
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16(mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+ u32 width;
+ width = get_sysboot_value();
+ if ((width & 0xF) == (BIT3 | BIT2)) {
+ return WIDTH_8BIT;
+ } else
+ return WIDTH_16BIT;
+
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return 1;
+ if (i == bound)
+ return 0;
+ } while (1);
+}
+
+/*****************************************************************
+ * is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+ u32 mux;
+ mux = get_sysboot_value();
+ if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+ return GPMC_MUXED; /* NAND Boot mode */
+ if (mux & BIT1) {/* if mux'ed */
+ return GPMC_MUXED;
+ } else
+ return GPMC_NONMUXED;
+}
+
+/*************************************************************************
+ * get_board_rev () - setup to pass board revision information
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+ /* Default Value as per now Poseidon Board have only one Revision */
+ return 0x01;
+}
+
+/*********************************************************************
+ * display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+ char *bootmode[] = {
+ "ONND",
+ "SIB1",
+ "SIB0",
+ "NAND",
+ "SIB1",
+ "SIB0",
+ "NOR",
+ "OneNAND",
+ };
+ u32 brev = get_board_rev();
+ char cpu_2430s[] = "2430C";
+ char db_ver[] = "0.0"; /* board type */
+ char mem_sdr[] = "mSDR"; /* memory type */
+ char mem_ddr[] = "mDDR";
+ char t_tst[] = "TST"; /* security level */
+ char t_emu[] = "EMU";
+ char t_hs[] = "HS";
+ char t_gp[] = "GP";
+ char unk[] = "?";
+ char t_poseidon[] = "POSEIDON";
+#ifdef CONFIG_LED_INFO
+ char led_string[CONFIG_LED_LEN] = { 0 };
+#endif
+
+#if defined(PRCM_CONFIG_I)
+ char prcm[] = "I";
+#elif defined(PRCM_CONFIG_II)
+ char prcm[] = "II";
+#endif
+ char *cpu_s, *db_s, *mem_s, *sec_s, *sdp;
+ u32 cpu, rev, sec;
+
+ rev = get_cpu_rev();
+ cpu = get_cpu_type();
+ sec = get_device_type();
+
+ if (is_mem_sdr()) {
+ mem_s = mem_sdr;
+ } else
+ mem_s = mem_ddr;
+
+ cpu_s = cpu_2430s;
+
+ db_s = db_ver;
+ db_s[0] += (brev >> 4) & 0xF;
+ db_s[2] += brev & 0xF;
+
+ switch (sec) {
+ case TST_DEVICE:
+ sec_s = t_tst;
+ break;
+ case EMU_DEVICE:
+ sec_s = t_emu;
+ break;
+ case HS_DEVICE:
+ sec_s = t_hs;
+ break;
+ case GP_DEVICE:
+ sec_s = t_gp;
+ break;
+ default:
+ sec_s = unk;
+ }
+
+ sdp = t_poseidon;
+
+ printf("OMAP%s-%s revision %d, PRCM %s\n", cpu_s, sec_s, rev, prcm);
+ printf("SAMSUNG %s %s Version + %s(Boot %s)\n", sdp, db_s,
+ mem_s, bootmode[get_gpmc0_type()]);
+#ifdef CONFIG_LED_INFO
+ /* Format: 0123456789ABCDEF
+ * 2430C GP#5A NAND
+ */
+ sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, prcm,
+ bootmode[get_gpmc0_type()]);
+ /* reuse sec */
+ for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) {
+ /* invert byte loc */
+ u16 val = led_string[sec] << 8;
+ val |= led_string[sec + 1];
+ __raw_writew(val, LED_REGISTER + sec);
+ }
+#endif
+
+}
+
+/********************************************************
+ * get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+ u32 val;
+ __asm__ __volatile__("mov %0, pc \n" : "=r"(val) : : "memory");
+ val &= 0xF0000000;
+ val >>= 28;
+ return val;
+}
+
+/********************************************************
+ * running_in_flash() - tell if currently running in
+ * flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+ if (get_base() < 4)
+ return 1; /* in flash */
+ return 0; /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ * running_in_sram() - tell if currently running in
+ * sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+ if (get_base() == 4)
+ return 1; /* in SRAM */
+ return 0; /* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ * running_in_sdram() - tell if currently running in
+ * flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+ if (get_base() > 4)
+ return 1; /* in sdram */
+ return 0; /* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ * running_from_internal_boot() - am I boot through mask rom.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+ u32 v;
+
+ v = get_sysboot_value() & (BIT2 | BIT1 | BIT0);
+ /* external boot settings bit1 == bit2 */
+ if (((v & BIT1) && (v & BIT2)) || (!(v & BIT1) && !(v & BIT2))) {
+ v = 0;
+ } else /* all other defined combos are internal */
+ v = 1;
+ return v;
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return mode >>= 8;
+}
diff --git a/board/poseidon/u-boot.lds b/board/poseidon/u-boot.lds
index e69de29..0dcc74d 100644
--- a/board/poseidon/u-boot.lds
+++ b/board/poseidon/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * Samsung Electronics, <www.samsung.com>
+ * Vivek Dalal <v.dalal at samsung.com>
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
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