[U-Boot] 88e61xx driver in u-boot

[Andrew Dyer]

Hi, I am in the midst of bringing up a board using the 88E6161 chip
and was looking at your u-boot driver as an example of how to set it
up (still writing simple tests loaded via JTAG, not the full u-boot).

Our board uses the indirect method of writing to the MII bus
registers, and I think there may be a bug in the indirect version of
mv88e61xx_rd_phy().  In the function, the command written into the SMI
indirect command register is:

  86        miiphy_write(name, mii_dev_addr, 0x0,
  87                      reg_ofs | (phy_adr << 5) | (1 << 10) | (1 <<
12) | (1 <<
  88
       15));

The part that looks wrong is the 1 << 10  (the SMIOp field).
According to the datasheet table 35, for a read to be performed inside
the chip it should be 2 << 10.  Probably cut and pasted from the
mv88e61xx_wr_phy() above.


I also wondered about this snippet of code:

  55 static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32
reg_ofs, u16 data)
  56 {
  57         u16 reg;
  58         u32 mii_dev_addr;
  59
  60         /* command to read PHY dev address */
  61         if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
  62                 printf("Error..could not read PHY dev address\n");
  63                return;
  64         }

I don't see anything in the 88E6161 switch itself that would respond
at those 0xEE addresses (IIRC the MII bus only provides for 5 bits of
register and phy address).  Is this something specific to the
board/SoC you were running the switch with and/or it's miiphy_read
implementation?

As far as I can tell, what is needed is to set mii_dev_addr to the
address set by the ADDR[4:0] chip config pins, which would see to be a
board specific item, and shouldn't be in the generic driver.  This
would seem like a good candidate for something that is passed in via
the mv88e61xx_config structure.