[U-Boot] [PATCH 3/7] 83xx/85xx/86xx: Add ECC support

[Liu Dave-R63238]

> > IIRC, 85xx cache is enabled, so when we do the ecc error 
> inject test,
> > What will happen before disable ecc error inject?
> > I-fetch may get wrong instruction?
> 
> and ....
> Because cache is enabled, data bus assume 64 bits (it is normal case).
> The DDR bus will have 4-beat burst. So the error information will be
> the last beat triggered, or multi-bit error at first beat....., or..
> It is really complex.....

BTW, 83xx are using the d-cache inhibited...
The ecc test code really has some tricks, eg: must interrupt disable
context,
var should be put in the registers....