[U-Boot] [PATCH] fsl-ddr: Fix power-down and ODT timing settings

[Liu Dave-R63238]

> 1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
>    It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
> 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
>    It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
>    We are setting the mode register MR0[A12]='1'
> 3. TIMING_CFG_5[RODT_ON] should be set to WL-2
> 4. TIMING_CFG_5[RODT_OFF] should be set to WL-1
> 5. TIMING_CFG_5[WODT_ON] should be set to WL-2
> 6. TIMING_CFG_5[WODT_OFF] should be set to WL-1
> 
> ps: WL=TIMING_CFG_2[WR_LAT]
> 
> The original work was finished by Mazyar Razzaz and Travis Wheatley.
> 
> Signed-off-by: Dave Liu <daveliu at freescale.com>
> Signed-off-by: Travis Wheatley <travis.wheatley at freescale.com>

Tested on MPC8569MDS board.