[U-Boot] [PATCH v3 3/3] ppc/p1_p2_RDB: DDR Relocation support for NAND/SD/eSPI Boot

[Kumar Gala]

On Oct 12, 2009, at 10:42 AM, Kim Phillips wrote:

> On Mon, 12 Oct 2009 12:01:32 +0530
> Dudhat Dipen-B09055 <Dipen.Dudhat at freescale.com> wrote:
>
>>> On Oct 9, 2009, at 12:42 PM, Dipen Dudhat wrote:
>>>
>>>> +void initsdram(void)
>>>> +{
>>>> +
>>>> +	volatile ccsr_ddr_t *ddr= (ccsr_ddr_t
>>> *)CONFIG_SYS_MPC85xx_DDR_ADDR;
>>>> +	int d_init, dbw;
>>>> +	volatile ccsr_gpio_t *pgpio = (void *)
>>>> (CONFIG_SYS_MPC85xx_GPIO_ADDR);
>>>> +	unsigned int ddr_size;
>>>> +	sys_info_t sysinfo;
>>>> +	phys_size_t dram_size = 0;
>>>> +
>>>> +	set_next_law(0,LAW_SIZE_1G , LAW_TRGT_IF_DDR_1);
>>>> +
>>>> +	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
>>>> +	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
>>>> +	out_be32(&ddr->cs0_config_2, CONFIG_SYS_DDR_CS0_CONFIG_2);
>>>> +
>>>> +	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
>>>> +	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
>>>> +	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
>>>> +	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
>>>> +	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
>>>> +	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
>>>> +	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
>>>> +	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
>>>> +	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
>>>> +	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
>>>
>>> did fsl_ddr_set_memctl_regs() not work?
>>>
>>> This function will take more space as we have only 4K space here.
>>> And this function contains 'printf' statements which is not valid.
>>>
>>> So I think this is the simplest approach, as  
>>> fsl_ddr_set_memctl_regs()
>>
>>> is doing the same thing.
>>> What do you suggest??
>>
>> We can dummy out the printf.  I'd prefer if we can try and use it.   
>> It
>> unifies the register setting in one place which is key.
>>
> On Mon, 12 Oct 2009 12:01:32 +0530
> Dudhat Dipen-B09055 <Dipen.Dudhat at freescale.com> wrote:
>
>> I have tried using "fsl_ddr_set_memctl_regs()".
>> But this can't get fit into 4K NAND_SPL Loader.
>
> by how much?  Have you tried using raw i/o accessors (__raw_writel and
> friends) instead of the usual out_be32, etc.?

with Kim on this, by how much.. or can you post the patch that does  
that and I can take a look.

- k