[U-Boot] esdmode for DDR2

[Kumar Gala]

5 is correct.

Here's an example:

rtt = 0x3:
esd_mode should be = 0x44:

         esdmode = (0
                 | ((rtt & 0x4) << 7)   /* rtt field is split */
                 | ((rtt & 0x2) << 5)   /* rtt field is split */
                 | ((rtt & 0x1) << 2)  /* rtt field is split */
                 );

         esdmode = (0
                 | ((0x3 & 0x4) << 7)   /* rtt field is split */
                 | ((0x3 & 0x2) << 5)   /* rtt field is split */
                 | ((0x3 & 0x1) << 2)  /* rtt field is split */
                 );

         esdmode = (0
                 | ((0) << 7)   /* rtt field is split */
                 | ((0x2) << 5)   /* rtt field is split */
                 | ((0x1) << 2)  /* rtt field is split */
                 );

         esdmode = (0
                 | (0x40)   /* rtt field is split */
                 | (0x4)  /* rtt field is split */
                 );

         esdmode = (0x44);

- k


On Oct 22, 2009, at 9:53 AM, Werner Nedel wrote:

> Sorry again,
>
> and with DDR2.
>
> On Thu, Oct 22, 2009 at 11:42 AM, Werner Nedel <wmnedel at gmail.com>  
> wrote:
>
>> Hi,
>>
>> sorry about that. I'm working on a MPC8548 platform and using the  
>> mpc8xxx
>> common code for DDR configuration.
>>
>>
>> On Thu, Oct 22, 2009 at 11:36 AM, Kumar Gala <galak at kernel.crashing.org 
>> >wrote:
>>
>>>
>>> On Oct 22, 2009, at 6:48 AM, Werner Nedel wrote:
>>>
>>> Hi,
>>>>
>>>> I was looking the ctrl_regs.c file at the last release of u-boot,
>>>> specifically at sdram_mode register, and checking at AN3369.pdf I  
>>>> think
>>>> that
>>>> Rtt bit position might be wrong. At the code, the bit shifting is  
>>>> 5, but
>>>> shouldn't be 6? I think that it overwrites AL register.
>>>>
>>>
>>> Can you be more specific about what arch/platform you are taking  
>>> about.
>>>
>>> - k
>>>
>>
>>
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