[U-Boot] [PATCH] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

[Dave Liu]

Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for these turnarounds.
Cutting down the turnaround from BL/2+4 to BL/2+2 will improve
the memory performance.

Signed-off-by: Dave Liu <daveliu at freescale.com>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 73f349f..27c58ed 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -948,9 +948,9 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 
 #if defined(CONFIG_FSL_DDR3)
-	/* We need set BL/2 + 4 for BC4 or OTF */
-	rrt = 4;	/* BL/2 + 4 clocks */
-	wwt = 4;	/* BL/2 + 4 clocks */
+	/* We need set BL/2 + 2 for BC4 or OTF */
+	rrt = 2;	/* BL/2 + 2 clocks */
+	wwt = 2;	/* BL/2 + 2 clocks */
 	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
 #endif
 	ddr->timing_cfg_4 = (0
-- 
1.6.4