[U-Boot] [PATCH] p2020ds: add alternate boot bank support using the ngPIXIS FPGA
Timur Tabi
timur at freescale.com
Mon Mar 22 23:18:29 CET 2010
The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS.
The ngPIXIS has one distinct new feature: the values of the on-board switches
can be selectively overridden with shadow registers. This feature is used to
boot from a different NOR flash bank, instead of having a register dedicated
for this purpose. Because the ngPIXIS is so different from the previous PIXIS,
a new file is introduced: ngpixis.c.
Also update the P2020DS checkboard() function to use the new macros defined
in the header file.
Signed-off-by: Timur Tabi <timur at freescale.com>
---
board/freescale/common/Makefile | 1 +
board/freescale/common/ngpixis.c | 136 +++++++++++++++++++++++++++++++++++++
board/freescale/p2020ds/p2020ds.c | 19 ++---
include/configs/P2020DS.h | 52 +++-----------
4 files changed, 155 insertions(+), 53 deletions(-)
create mode 100644 board/freescale/common/ngpixis.c
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 02a824d..620eb16 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -33,6 +33,7 @@ COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
COBJS-${CONFIG_FSL_VIA} += cds_via.o
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
+COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
new file mode 100644
index 0000000..93e2a03
--- /dev/null
+++ b/board/freescale/common/ngpixis.c
@@ -0,0 +1,136 @@
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard. It contains
+ * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches. There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ * is used in the PIXIS_SW() macro to determine which offset in
+ * the PIXIS register map corresponds to the physical switch that controls
+ * the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ * boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void pixis_reset(void)
+{
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+}
+
+/*
+ * Reset the board. Like pixis_reset(), but it honors the ENx registers.
+ */
+void pixis_bank_reset(void)
+{
+ out8(PIXIS_BASE + PIXIS_VCTL, 0);
+ out8(PIXIS_BASE + PIXIS_VCTL, 1);
+}
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void clear_altbank(void)
+{
+ /* Tell the ngPIXIS to use this the bits in the physical switch for the
+ * boot bank value, instead of the SWx register. We need to be careful
+ * only to set the bits in SWx that correspond to the boot bank.
+ */
+ clrbits_8((void *)PIXIS_BASE + PIXIS_EN(PIXIS_LBMAP_SWITCH),
+ PIXIS_LBMAP_MASK);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void set_altbank(void)
+{
+ /* Program the alternate bank number into the SWx register.
+ */
+ clrsetbits_8((void *)PIXIS_BASE + PIXIS_SW(PIXIS_LBMAP_SWITCH),
+ PIXIS_LBMAP_MASK, PIXIS_LBMAP_ALTBANK);
+
+ /* Tell the ngPIXIS to use this the bits in the SWx register for the
+ * boot bank value, instead of the physical switch. We need to be
+ * careful only to set the bits in SWx that correspond to the boot bank.
+ */
+ setbits_8((void *)PIXIS_BASE + PIXIS_EN(PIXIS_LBMAP_SWITCH),
+ PIXIS_LBMAP_MASK);
+}
+
+
+int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int i;
+ char *p_altbank = NULL;
+ char *unknown_param = NULL;
+
+ /*
+ * No args is a simple reset request.
+ */
+ if (argc <= 1)
+ pixis_reset();
+ /* not reached */
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "altbank") == 0) {
+ p_altbank = argv[i];
+ continue;
+ }
+
+ unknown_param = argv[i];
+ }
+
+ if (unknown_param) {
+ printf("Invalid option: %s\n", unknown_param);
+ return 1;
+ }
+
+ if (p_altbank)
+ set_altbank();
+ else
+ clear_altbank();
+
+ pixis_bank_reset();
+
+ /*
+ * Shouldn't be reached.
+ */
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+ "Reset the board using the FPGA sequencer",
+ " pixis_reset\n"
+ " pixis_reset [altbank]\n"
+ );
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 664135c..1eb2dfb 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -59,17 +59,14 @@ int checkboard(void)
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
- sw7 = in_8(pixis_base + PIXIS_SW(7));
- switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
- case 0:
- case 1:
- printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
- break;
- case 2:
- case 3:
- puts ("Promjet\n");
- break;
- }
+ sw7 = in_8(pixis_base + PIXIS_SW(PIXIS_LBMAP_SWITCH));
+ sw7 = (sw7 & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+ if (sw7 < 0x8)
+ /* The lower two bits are the actual vbank number */
+ printf("vBank: %d\n", sw7 & 3);
+ else
+ puts("Promjet\n");
return 0;
}
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 30a5a31..33e7a4f 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
+#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
+
+#ifdef CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
@@ -252,21 +254,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
@@ -274,34 +263,13 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
-#define PIXIS_LED 0x25 /* LED Register */
-
-#define PIXIS_SW(x) 0x20 + (x - 1) * 2
-#define PIXIS_EN(x) 0x21 + (x - 1) * 2
-#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
-#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
-#define PIXIS_VSPEED2_TSEC1SER 0x8
-#define PIXIS_VSPEED2_TSEC2SER 0x4
-#define PIXIS_VSPEED2_TSEC3SER 0x2
-#define PIXIS_VSPEED2_TSEC4SER 0x1
-#define PIXIS_VCFGEN1_TSEC1SER 0x20
-#define PIXIS_VCFGEN1_TSEC2SER 0x20
-#define PIXIS_VCFGEN1_TSEC3SER 0x20
-#define PIXIS_VCFGEN1_TSEC4SER 0x20
-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
- | PIXIS_VSPEED2_TSEC2SER \
- | PIXIS_VSPEED2_TSEC3SER \
- | PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
- | PIXIS_VCFGEN1_TSEC2SER \
- | PIXIS_VCFGEN1_TSEC3SER \
- | PIXIS_VCFGEN1_TSEC4SER)
+#define PIXIS_SW(x) (0x20 + (x - 1) * 2)
+#define PIXIS_EN(x) (0x21 + (x - 1) * 2)
+#define PIXIS_LBMAP_SWITCH 7
+#define PIXIS_LBMAP_MASK 0xf0
+#define PIXIS_LBMAP_SHIFT 4
+#define PIXIS_LBMAP_ALTBANK 0x20
+#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
--
1.6.5
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