[U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

Shaohui Xie b21989 at freescale.com
Tue Nov 16 09:48:05 CET 2010


PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC
after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan <b25806 at freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu at freescale.com>
Signed-off-by: Shaohui Xie <b21989 at freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c  |   17 +++++++++++++++++
 board/freescale/corenet_ds/config.mk |    6 ++++++
 board/freescale/corenet_ds/tlb.c     |    9 +++++++++
 boards.cfg                           |    1 +
 include/configs/corenet_ds.h         |   31 +++++++++++++++++++++++++++++--
 5 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 27236a0..cff7ac3 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -139,6 +139,20 @@ static void enable_cpc(void)
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
 		size += CPC_CFG0_SZ_K(cpccfg0);
+		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
+			/* find and disable LAW of SRAM */
+			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+			if (law.index == -1) {
+				printf("\nFatal error happened\n");
+				return;
+			} else
+				disable_law(law.index);
+
+			clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+			out_be32(&cpc->cpccsr0, 0);
+			out_be32(&cpc->cpcsrcr0, 0);
+		}
 
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
@@ -155,6 +169,9 @@ void invalidate_cpc(void)
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+		/* skip CPC when it used as all SRAM */
+		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
+			continue;
 		/* Flash invalidate the CPC and clear all the locks */
 		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk
index 15bbf20..31b3379 100644
--- a/board/freescale/corenet_ds/config.mk
+++ b/board/freescale/corenet_ds/config.mk
@@ -24,4 +24,10 @@
 # P4080DS board
 #
 
+ifeq ($(CONFIG_PBL_BOOT_INDIRECT), y)
+RESET_VECTOR_ADDRESS = 0xfffffffc
+endif
+
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffffffc
+endif
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..08f91a7 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 * */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/boards.cfg b/boards.cfg
index 6c2a667..168d6f5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -195,6 +195,7 @@ P1022DS		powerpc	mpc85xx		p1022ds		freescale
 P2020DS		powerpc	mpc85xx		p2020ds		freescale
 stxgp3		powerpc	mpc85xx		stxgp3		stx
 P4080DS		powerpc	mpc85xx		corenet_ds	freescale
+P4080DS_PBL_BOOT_INDIRECT	powerpc	mpc85xx		corenet_ds	freescale	-	P4080DS:PBL_BOOT_INDIRECT,SYS_TEXT_BASE=0xFFF80000
 sbc8540		powerpc	mpc85xx		sbc8560		-		-	SBC8540
 sbc8548		powerpc	mpc85xx		sbc8548		-		-	sbc8548
 sbc8560		powerpc	mpc85xx		sbc8560		-		-	sbc8560
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 2ac59e5..0776c3b 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -28,6 +28,11 @@
 
 #include "../board/freescale/common/ics307_clk.h"
 
+#ifdef CONFIG_PBL_BOOT_INDIRECT
+#define CONFIG_RAMBOOT_PBL		1
+#define CONFIG_RAMBOOT_TEXT_BASE        0xfff80000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -58,11 +63,17 @@
 #ifdef CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_NOWHERE
 #else
-#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL)
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#else
+	#define CONFIG_ENV_IS_IN_FLASH
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 
@@ -93,6 +104,19 @@
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+
+/*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
@@ -185,6 +209,10 @@
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
 
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
@@ -456,7 +484,6 @@
 /*
  * Environment
  */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 
-- 
1.6.4




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