[U-Boot] [PATCH] ppc4xx: Fix build problems of IBM DDR2 NAND booting targets

[Stefan Roese]

This change is needed to compile the PPC4xx NAND booting targets
equipped with the IBM DDR2 SDRAM controller.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Wolfgang Denk <wd at denx.de>
---
Wolfgang, this patch is needed to build the 44x NAND booting targets.
Its based on top of your patchset "[PATCH 0/7] Address partial linking
issues". How should we best handle these patches to make this git
bisectable? Feel free to squash this patch into your patches to make
this easier.

Thanks,
Stefan

 arch/powerpc/cpu/ppc4xx/Makefile     |    2 +-
 board/amcc/canyonlands/canyonlands.c |   12 ------------
 2 files changed, 1 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile
index 93ebf89..d97ca20 100644
--- a/arch/powerpc/cpu/ppc4xx/Makefile
+++ b/arch/powerpc/cpu/ppc4xx/Makefile
@@ -37,9 +37,9 @@ COBJS	:= 40x_spd_sdram.o
 ifndef CONFIG_NAND_SPL
 ifndef CONFIG_NAND_U_BOOT
 COBJS	+= 44x_spd_ddr.o
-COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
 endif
 endif
+COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
 COBJS-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
 COBJS	+= 4xx_pci.o
 COBJS	+= 4xx_pcie.o
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index faa3720..80e2739 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -363,18 +363,6 @@ int checkboard(void)
 }
 #endif	/* !defined(CONFIG_ARCHES) */
 
-#if defined(CONFIG_NAND_U_BOOT)
-/*
- * NAND booting U-Boot version uses a fixed initialization, since the whole
- * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
- * code.
- */
-phys_size_t initdram(int board_type)
-{
-	return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
-#endif
-
 #if defined(CONFIG_PCI)
 int board_pcie_first(void)
 {
-- 
1.7.3.2