[U-Boot] Question about PCIe configuration

[Carlos Roberto Moratelli]

Em Qui, 2010-10-07 às 09:33 -0500, Swarthout Edward L-SWARTHOU escreveu:
> The LTSSM value of 8 indicates the problem.  See:
> 
> "Table 18-111. PEX_LTSSM_STAT Status Codes"
>  8 - "Polling compliance"
> 
> This shows the 8536 is fine and detects the device's receivers on the
> bus, but the device has not responded with a correct training
> sequence.
> 
> There are many potential causes for the device not responding:
> 1. device powered on?
> 2. have correct clocks?
> 3. if an fpga, is it loaded?
> 4. is it out of reset?

I am considering a hardware design issue too, the hardware team is
working on that.

> 
> What is the device?  Can you query it with a jtag probe?
> 
> >     PCIE1 on bus 01 - 01
> > 
> > I was expecting to find a peripherical on PCIE1 bus. I have a
> switch 
> > chip connected to Serdes 1 lane A.
> 
> I see.  What switch?  Is it on a card or directly on the board?
> Can you probe reset,  power, and clocks?

A broadcom switch. It is directly on the board. 

I tried to probe SD1_PLL_TPD (PLL test point Digital, pin V28 on MPC8536
E), there is no signal there. What Should I observe in this pin? I was
expecting to observe the internal serdes clock signal. 

Thanks

Carlos R. Moratelli