[U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes

[Kumar Gala]

On Apr 10, 2011, at 10:30 AM, Stefano Babic wrote:

> On 03/07/2011 05:14 AM, Kumar Gala wrote:
>> From: Priyanka Jain <Priyanka.Jain at freescale.com>
>> 
>> P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
>> level register description has been changed:
>> 
>> 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
>> 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
>> 
>> Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
>> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal at freescale.com>
>> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>> ---
> 
> Tested on i.MX51.
> 
> Tested-by: Stefano Babic <sbabic at denx.de>

applied to 85xx

- k