[U-Boot] [PATCH 2/2] MIPS: Coding style cleanups on common assembly files

[Daniel Schwierzeck]

Hi Shinya,

I have some minor additions

2011/4/9 Shinya Kuribayashi <skuribay at pobox.com>:
> Fix style issues and alignments globally.  No logical changes.
> - Replace C comments with AS line comments where possible
> - Use ifndef where possible, rather than if !defined for simplicity
> - An instruction executed in a delay slot is now indicated by a leading
>  space, not by C comment
>
> Signed-off-by: Shinya Kuribayashi <skuribay at pobox.com>
> ---
>  arch/mips/cpu/mips32/cache.S |   81 ++++++++++++++---------------
>  arch/mips/cpu/mips32/start.S |  117 +++++++++++++++++++----------------------
>  2 files changed, 92 insertions(+), 106 deletions(-)
>
> diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S

[...]

> diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
> index 0a9d9d5..f1e3447 100644
> --- a/arch/mips/cpu/mips32/start.S
> +++ b/arch/mips/cpu/mips32/start.S
> @@ -62,11 +62,11 @@
>        .globl _start
>        .text
>  _start:
> -       RVECENT(reset,0)        /* U-boot entry point */
> -       RVECENT(reset,1)        /* software reboot */
> -#if defined(CONFIG_INCA_IP)
> -       .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
> -       .word 0x00000000           /* phase of the flash                    */
> +       RVECENT(reset,0)                        # U-boot entry point
> +       RVECENT(reset,1)                        # software reboot
> +#ifdef CONFIG_INCA_IP
> +       .word INFINEON_EBU_BOOTCFG              # EBU init code, fetched during
> +       .word 0x00000000                        # booting phase of the flash
>  #else
>        RVECENT(romReserved,2)
>  #endif

can we use #ifdef INFINEON_EBU_BOOTCFG instead? This would help me
with other SOCs which uses this feature too.

> @@ -131,7 +131,7 @@ _start:
>        RVECENT(romReserved,61)
>        RVECENT(romReserved,62)
>        RVECENT(romReserved,63)
> -       XVECENT(romExcHandle,0x200)     /* bfc00200: R4000 tlbmiss vector */
> +       XVECENT(romExcHandle,0x200)     # bfc00200: R4000 tlbmiss vector
>        RVECENT(romReserved,65)
>        RVECENT(romReserved,66)
>        RVECENT(romReserved,67)
> @@ -147,7 +147,7 @@ _start:
>        RVECENT(romReserved,77)
>        RVECENT(romReserved,78)
>        RVECENT(romReserved,79)
> -       XVECENT(romExcHandle,0x280)     /* bfc00280: R4000 xtlbmiss vector */
> +       XVECENT(romExcHandle,0x280)     # bfc00280: R4000 xtlbmiss vector
>        RVECENT(romReserved,81)
>        RVECENT(romReserved,82)
>        RVECENT(romReserved,83)
> @@ -163,7 +163,7 @@ _start:
>        RVECENT(romReserved,93)
>        RVECENT(romReserved,94)
>        RVECENT(romReserved,95)
> -       XVECENT(romExcHandle,0x300)     /* bfc00300: R4000 cache vector */
> +       XVECENT(romExcHandle,0x300)     # bfc00300: R4000 cache vector
>        RVECENT(romReserved,97)
>        RVECENT(romReserved,98)
>        RVECENT(romReserved,99)

you missed that line:
XVECENT(romExcHandle,0x380) 	/* bfc00380: R4000 general vector */

> @@ -196,19 +196,19 @@ _start:
>        RVECENT(romReserved,126)
>        RVECENT(romReserved,127)
>
> -       /* We hope there are no more reserved vectors!
> +       /*
> +        * We hope there are no more reserved vectors!
>         * 128 * 8 == 1024 == 0x400
>         * so this is address R_VEC+0x400 == 0xbfc00400
>         */
>        .align 4
>  reset:
>
> -       /* Clear watch registers.
> -        */
> +       /* Clear watch registers */
>        mtc0    zero, CP0_WATCHLO
>        mtc0    zero, CP0_WATCHHI

[...]

Best regards
Daniel