[U-Boot] [PATCH v3 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support

Graeme Russ graeme.russ at gmail.com
Thu Jan 20 01:20:41 CET 2011


On Thu, Jan 20, 2011 at 8:19 AM, Tom Warren <twarren.nvidia at gmail.com> wrote:

> +
> +/*
> + * Routine: uart_clock_init
> + * Description: init the PLL and clock for the UART in uart_num
> + */
> +void uart_clock_init(int uart_num)
> +{
> +       clk_rst_ctlr *const clkrst = (clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
> +       static int pllp_init_done;
> +       u32 reg;
> +
> +       if (!pllp_init_done) {
> +
> +               /* Override pllp setup for 216MHz operation. */
> +               reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
> +               reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
> +               writel(reg, clkrst->crc_pllp_base);
> +
> +               reg |= PLL_ENABLE;
> +               writel(reg, clkrst->crc_pllp_base);

Is this correct? Should it not be writel(reg, &clkrst->crc_pllp_base);

Similarly for other readl()'s and writel()'s

Regards,

Graeme


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