[U-Boot] [RESEND PATCH v2 1/5] Tegra2: Add macros to calculate bitfield shifts and masks

[Wolfgang Denk]

Dear Anton Staaf,

In message <CAF6FioVOEuNcEsr=3jyxoVs__dO3Ox+q00PnDBRHdu+UmJZF2g at mail.gmail.com> you wrote:
>
> In both cases the value 20 needs to come from somewhere.  So you would
> probably end up having:
> 
>    #define SCFR1_IPS_DIV_MASK      0x03800000
>    #define SCFR1_IPS_DIV_SHIFT      20
> 
> and
> 
>    (value & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT
>    (value & ~SCFR1_IPS_DIV_MASK) | (5 << SCFR1_IPS_DIV_SHIFT)

BTW - you are correct about this.  The file I grabbed the examples
from is "arch/powerpc/include/asm/immap_512x.h"; here is the full
context:

 229 /* SCFR1 System Clock Frequency Register 1 */
 230 #define SCFR1_IPS_DIV           0x3
 231 #define SCFR1_IPS_DIV_MASK      0x03800000
 232 #define SCFR1_IPS_DIV_SHIFT     23
 233
 234 #define SCFR1_PCI_DIV           0x6
 235 #define SCFR1_PCI_DIV_MASK      0x00700000
 236 #define SCFR1_PCI_DIV_SHIFT     20
 237
 238 #define SCFR1_LPC_DIV_MASK      0x00003800
 239 #define SCFR1_LPC_DIV_SHIFT     11
 240
 241 /* SCFR2 System Clock Frequency Register 2 */
 242 #define SCFR2_SYS_DIV           0xFC000000
 243 #define SCFR2_SYS_DIV_SHIFT     26

And indeed we see code using this for example in
arch/powerpc/cpu/mpc512x/speed.c:

 98         reg = in_be32(&im->clk.scfr[0]);
 99         ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;

The nice thing (for me) here is, that without even thinking for a
second I know exactly what is going on - there is nothing in this
statements that require me too look up some macro definition. [Yes,
of course this is based on the assumption that macro names
<register>_MASK and <register>_SHIFT just do what they are suggest
they are doing.  But any such things get filtered out during the
reviews.]

Best regards,

Wolfgang Denk

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