[U-Boot] [PATCH v2] AT91: pio: Add PIO3 features

Hong Xu hong.xu at atmel.com
Mon Nov 14 06:01:59 CET 2011


This patch adds the support for new PIO controller introduced by some
AT91 SoCs.

New features include
* More peripheral multiplexing
* Pull-down, Schmitt trigger, Debouncer
* More irq trigger mode (may be not interesting in U-Boot)

Signed-off-by: Hong Xu <hong.xu at atmel.com>
---
    - Correct register group definitions
    - ATMEL_CPU_HAS_PIO3 -> CONFIG_CPU_HAS_PIO3

 arch/arm/include/asm/arch-at91/at91_pio.h |   48 ++++++++++-
 drivers/gpio/at91_gpio.c                  |  130 +++++++++++++++++++++++++++-
 2 files changed, 171 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h
index 416cabf..90a3ad6 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -4,6 +4,7 @@
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
  * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ * Copyright (C) 2011 Hong Xu (hong.xu at atmel.com)
  *
  * Parallel I/O Controller (PIO) - System peripherals registers.
  * Based on AT91RM9200 datasheet revision E.
@@ -17,7 +18,6 @@
 #ifndef AT91_PIO_H
 #define AT91_PIO_H
 
-
 #define AT91_ASM_PIO_RANGE	0x200
 #define AT91_ASM_PIOC_ASR	\
 	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
@@ -66,14 +66,51 @@ typedef struct at91_port {
 	u32	puer;		/* 0x64 Pull-up Enable Register */
 	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
 	u32	reserved4;
+#if defined(CONFIG_CPU_HAS_PIO3)
+	u32	abcdsr1;	/* 0x70 Peripheral ABCD Select Register 1 */
+	u32	abcdsr2;	/* 0x74 Peripheral ABCD Select Register 2 */
+	u32	reserved5[2];
+	u32	ifscdr;		/* 0x80 Input Filter SCLK Disable Register */
+	u32	ifscer;		/* 0x84 Input Filter SCLK Enable Register */
+	u32	ifscsr;		/* 0x88 Input Filter SCLK Status Register */
+	u32	scdr;		/* 0x8C SCLK Divider Debouncing Register */
+#define PIO_SCDR_DIV_MASK	(0x3fff <<  0)	/* Slow Clock Divider Mask */
+	u32	ppddr;		/* 0x90 Pad Pull-down Disable Register */
+	u32	ppder;		/* 0x94 Pad Pull-down Enable Register */
+	u32	ppdsr;		/* 0x98 Pad Pull-down Status Register */
+	u32	reserved6;
+#else
 	u32	asr;		/* 0x70 Select A Register */
 	u32	bsr;		/* 0x74 Select B Register */
 	u32	absr;		/* 0x78 AB Select Status Register */
 	u32	reserved5[9];	/*  */
+#endif
 	u32	ower;		/* 0xA0 Output Write Enable Register */
 	u32	owdr;		/* 0xA4 Output Write Disable Register */
-	u32	owsr;		/* OxA8 utput Write Status Register */
+	u32	owsr;		/* OxA8 Output Write Status Register */
+#if defined(CONFIG_CPU_HAS_PIO3)
+	u32	reserved7;	/*  */
+	u32	aimer;		/* Additional Interrupt Modes Enable Register*/
+	u32	aimdr;		/* Additional Interrupt Modes Disable Register*/
+	u32	aimmr;		/* Additional Intterupt Modes Mask Register */
+	u32	reserved8;	/* */
+	u32	esr;		/* 0xC0 Edge Select Register */
+	u32	lsr;		/* 0xC4 Level Select Register */
+	u32	elsr;		/* 0xC8 Edge/Level Status Register */
+	u32	reserved9;	/* 0xCC */
+	u32	fellsr;		/* 0xD0 Falling Edge/Low Level Select Register*/
+	u32	rehlsr;		/* 0xD4 Rising Edge/High Level Select Register*/
+	u32	frlhsr;		/* 0xD8 Fall/Rise - Low/High Status Register */
+	u32	reserved10;	/* */
+	u32	locksr;		/* 0xE0 Lock Status */
+	u32	wpmr;		/* 0xE4 Write Protect Mode Register */
+	u32	wpsr;		/* 0xE4 Write Protect Status Register */
+	u32	reserved11[5];	/* */
+	u32	schmitt;	/* 0x100 Schmitt Trigger Register */
+	u32	reserved12[63];
+#else
 	u32	reserved6[85];
+#endif
 } at91_port_t;
 
 typedef union at91_pio {
@@ -94,6 +131,13 @@ typedef union at91_pio {
 #ifdef CONFIG_AT91_GPIO
 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(CONFIG_CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
 int at91_set_pio_output(unsigned port, unsigned pin, int value);
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index be2a026..d85f3e3 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -1,6 +1,8 @@
 /*
  * Memory Setup stuff - taken from blob memsetup.S
  *
+ * Copyright (C) 2011 Hong Xu (hong.xu at atmel.com)
+ *
  * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
  *
  *  Copyright (C) 2005 HP Labs
@@ -58,7 +60,7 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
 }
 
 /*
- * mux the pin to the "GPIO" peripheral role.
+ * mux the pin to the "GPIO" peripheral function.
  */
 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
 {
@@ -75,7 +77,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
 }
 
 /*
- * mux the pin to the "A" internal peripheral role.
+ * mux the pin to the "A" internal peripheral function.
  */
 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
 {
@@ -86,14 +88,21 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
 		mask = 1 << pin;
 		writel(mask, &pio->port[port].idr);
 		at91_set_pio_pullup(port, pin, use_pullup);
+#if defined(CONFIG_CPU_HAS_PIO3)
+		writel(readl(&pio->port[port].abcdsr1) & ~mask,
+			&pio->port[port].abcdsr1);
+		writel(readl(&pio->port[port].abcdsr2) & ~mask,
+			&pio->port[port].abcdsr2);
+#else
 		writel(mask, &pio->port[port].asr);
+#endif
 		writel(mask, &pio->port[port].pdr);
 	}
 	return 0;
 }
 
 /*
- * mux the pin to the "B" internal peripheral role.
+ * mux the pin to the "B" internal peripheral function.
  */
 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
 {
@@ -104,13 +113,120 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
 		mask = 1 << pin;
 		writel(mask, &pio->port[port].idr);
 		at91_set_pio_pullup(port, pin, use_pullup);
+#if defined(CONFIG_CPU_HAS_PIO3)
+		writel(readl(&pio->port[port].abcdsr1) | mask,
+			&pio->port[port].abcdsr1);
+		writel(readl(&pio->port[port].abcdsr2) & ~mask,
+			&pio->port[port].abcdsr2);
+#else
 		writel(mask, &pio->port[port].bsr);
+#endif
+		writel(mask, &pio->port[port].pdr);
+	}
+	return 0;
+}
+
+#if defined(CONFIG_CPU_HAS_PIO3)
+/*
+ * mux the pin to the "C" internal peripheral function.
+ */
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
+{
+	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
+	u32		mask;
+
+	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+		mask = 1 << pin;
+		writel(mask, &pio->port[port].idr);
+		at91_set_pio_pullup(port, pin, use_pullup);
+		writel(readl(&pio->port[port].abcdsr1) & ~mask,
+			&pio->port[port].abcdsr1);
+		writel(readl(&pio->port[port].abcdsr2) | mask,
+			&pio->port[port].abcdsr2);
 		writel(mask, &pio->port[port].pdr);
 	}
 	return 0;
 }
 
 /*
+ * mux the pin to the "D" internal peripheral function.
+ */
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
+{
+	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
+	u32		mask;
+
+	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+		mask = 1 << pin;
+		writel(mask, &pio->port[port].idr);
+		at91_set_pio_pullup(port, pin, use_pullup);
+		writel(readl(&pio->port[port].abcdsr1) | mask,
+			&pio->port[port].abcdsr1);
+		writel(readl(&pio->port[port].abcdsr2) | mask,
+			&pio->port[port].abcdsr2);
+		writel(mask, &pio->port[port].pdr);
+	}
+	return 0;
+}
+
+/*
+ * enable/disable the debounce filter.
+ */
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
+{
+	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
+
+	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+		if (is_on) {
+			writel(1 << pin, &pio->port[port].ifscer);
+			writel(div & PIO_SCDR_DIV_MASK, &pio->port[port].scdr);
+			writel(1 << pin, &pio->port[port].ifer);
+		} else {
+			writel(1 << pin, &pio->port[port].ifdr);
+		}
+	}
+	return 0;
+}
+
+/*
+ * enable/disable the pull-down.
+ * If pull-up already enabled while calling the function, we disable it.
+ */
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_pulldown)
+{
+	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
+
+	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+		writel(1 << pin, &pio->port[port].pudr);
+		if (is_pulldown)
+			writel(1 << pin, &pio->port[port].ppder);
+		else
+			writel(1 << pin, &pio->port[port].ppddr);
+	}
+	return 0;
+}
+
+/*
+ * Set Schmitt trigger mode
+ */
+int at91_set_pio_schmitt_trig(unsigned port, unsigned pin, int is_enabled)
+{
+	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	u32		data;
+
+	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+		data = readl(&pio->port[port].schmitt);
+		if (is_enabled)
+			data &= ~(1 << pin);
+		else
+			data |= (1 << pin);
+		writel(data, &pio->port[port].schmitt);
+	}
+	return 0;
+}
+#endif
+
+/*
  * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
  * configure it for an input.
  */
@@ -162,10 +278,14 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
 		mask = 1 << pin;
-		if (is_on)
+		if (is_on) {
+#if defined(CONFIG_CPU_HAS_PIO3)
+			writel(mask, &pio->port[port].ifscdr);
+#endif
 			writel(mask, &pio->port[port].ifer);
-		else
+		} else {
 			writel(mask, &pio->port[port].ifdr);
+		}
 	}
 	return 0;
 }
-- 
1.7.3.3



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