[U-Boot] [PATCH 2/4] arm, omap3: Add support for TechNexion modules
Igor Grinberg
grinberg at compulab.co.il
Mon Nov 21 10:19:23 CET 2011
Hi Tapani,
I think, most of the comments below apply to all the patches in the series.
Seems, like subject should be:
arm: omap3: ....
On 11/21/11 10:44, Tapani Utriainen wrote:
>
> Add support for TechNexion TAM3517 SoM
This is a very short commit message.
>
> Signed-off-by: Tapani Utriainen <tapani at technexion.com>
> CC: Sandeep Paulraj <s-paulraj at ti.com>
> ---
> arch/arm/include/asm/mach-types.h | 1
> board/technexion/tam3517/Makefile | 49 ++++
> board/technexion/tam3517/tam3517.c | 150 ++++++++++++
> board/technexion/tam3517/tam3517.h | 388 +++++++++++++++++++++++++++++++++
> boards.cfg | 1
> include/configs/tam3517.h | 427 +++++++++++++++++++++++++++++++++++++
MAINTAINERS file should be updated.
> 6 files changed, 1016 insertions(+)
>
> diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
> index 2d5c3bc..685b46f 100644
> --- a/arch/arm/include/asm/mach-types.h
> +++ b/arch/arm/include/asm/mach-types.h
> @@ -467,6 +467,7 @@ extern unsigned int __machine_arch_type;
> #define MACH_TYPE_OMAP4_PANDA 2791
> #define MACH_TYPE_TI8168EVM 2800
> #define MACH_TYPE_TETON_BGA 2816
> +#define MACH_TYPE_TAM3517 2818
> #define MACH_TYPE_EUKREA_CPUIMX25SD 2820
> #define MACH_TYPE_EUKREA_CPUIMX35SD 2821
> #define MACH_TYPE_EUKREA_CPUIMX51SD 2822
This is wrong!
If your machine type is missing from the mach-types file,
then use your board configuration file to define the machine type.
> diff --git a/board/technexion/tam3517/Makefile b/board/technexion/tam3517/Makefile
> new file mode 100644
> index 0000000..2c10f4b
> --- /dev/null
> +++ b/board/technexion/tam3517/Makefile
> @@ -0,0 +1,49 @@
> +#
> +# (C) Copyright 2000, 2001, 2002
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := $(BOARD).o
> +
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +clean:
> + rm -f $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak $(obj).depend
clean and distclean targets have no use, please, remove.
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/technexion/tam3517/tam3517.c b/board/technexion/tam3517/tam3517.c
> new file mode 100644
> index 0000000..45a066a
> --- /dev/null
> +++ b/board/technexion/tam3517/tam3517.c
> @@ -0,0 +1,150 @@
> +/*
> + * Maintainer: TechNexion Linux FAE Group <linuxfae at technexion.com>
> + *
> + * This file provides support for TechNexion TAM3517 SoM
> + * It has been tested using a Twister baseboard.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
Postal address is subject to change. Will you be around when
it will change next time? Is this a correct address at all?
Probably, the best would be to remove the sentence with the address.
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <nand.h>
> +#include <asm/io.h>
> +#include <asm/arch/mmc_host_def.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/mux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/omap_gpmc.h>
> +#include <i2c.h>
> +#include <asm/mach-types.h>
> +#include "tam3517.h"
> +
> +#define AM3517_IP_SW_RESET 0x48002598
> +#define CPGMACSS_SW_RST (1 << 1)
There is a patch [1] pending for this to be done in a board independent way.
Please, wait until it gets merged or rebase on top of it and specify this
as a dependency.
Albert,
What's the status of the patch below?
[1] http://patchwork.ozlabs.org/patch/125032/
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
> +
> + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> + /* board id for Linux */
> + gd->bd->bi_arch_number = MACH_TYPE_TAM3517;
Use common code facilities to setup the machine type.
See CONFIG_MACH_TYPE in the README file.
> + /* boot param addr */
> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> +#if defined(CONFIG_XR16L2751)
> + writel(0x00000000, &gpmc_cfg->cs[1].config1);
> + writel(0x001e1e01, &gpmc_cfg->cs[1].config2);
> + writel(0x00080300, &gpmc_cfg->cs[1].config3);
> + writel(0x1c091c09, &gpmc_cfg->cs[1].config4);
> + writel(0x04181f1f, &gpmc_cfg->cs[1].config5);
> + writel(0x00000FCF, &gpmc_cfg->cs[1].config6);
> + writel(0x00000f61, &gpmc_cfg->cs[1].config7);
> +
> + writel(0x00000000, &gpmc_cfg->cs[3].config1);
> + writel(0x001e1e01, &gpmc_cfg->cs[3].config2);
> + writel(0x00080300, &gpmc_cfg->cs[3].config3);
> + writel(0x1c091c09, &gpmc_cfg->cs[3].config4);
> + writel(0x04181f1f, &gpmc_cfg->cs[3].config5);
> + writel(0x00000FCF, &gpmc_cfg->cs[3].config6);
> + writel(0x00000f63, &gpmc_cfg->cs[3].config7);
> +#endif
> + return 0;
> +}
> +
> +/*
> + * Routine: misc_init_r
> + */
> +int misc_init_r(void)
> +{
> + int ctr = 0;
> +
> + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
This is already done in the common code, why do you need
this called here again?
> +#ifdef CONFIG_BOOT_FROM_MMC
> + omap_set_gpio_direction(TAM3517_SW3_PIN8, 1);
> +#endif
> +
> +#if defined(CONFIG_DRIVER_TI_EMAC)
> + /* allow the PHY to stabilize and settle down */
> + do {
> + udelay(1000);
> + ctr++;
> + } while (ctr < 300);
> +
> + /*ensure that the module is out of reset*/
> + reset = readl(AM3517_IP_SW_RESET);
> + reset &= (~CPGMACSS_SW_RST);
> + writel(reset, AM3517_IP_SW_RESET);
> +#endif
This also should wait for the patch in the link above.
> + dieid_num_r();
> + return 0;
> +}
> +
> +
> +/*
> + * Initializes on-chip ethernet controllers.
> + * to override, implement board_eth_init()
The comment does not apply here ....
> + */
> +int board_eth_init(bd_t *bis)
> +{
> + int n_eth = 0;
What's the use for that variable?
> +
> +#if defined(CONFIG_DRIVER_TI_EMAC)
> + davinci_emac_initialize();
> + n_eth++;
> +#endif
> +
> +
> +#if defined(CONFIG_SMC911X)
> + /* init cs for extern lan */
> + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
> + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
> + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
> + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
> + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
> + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
> + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
> +
> + if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
> + n_eth--;
> +#endif
> + return 0;
> +}
> +
> +
> +#ifdef CONFIG_GENERIC_MMC
> +int board_mmc_init(bd_t *bis)
> +{
> + omap_mmc_init(0);
> + return 0;
Why not:
return omap_mmc_init(0);
?
> +}
> +#endif
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{
> + MUX_TAM3517();
> +}
> diff --git a/board/technexion/tam3517/tam3517.h b/board/technexion/tam3517/tam3517.h
> new file mode 100644
> index 0000000..6b77fba
> --- /dev/null
> +++ b/board/technexion/tam3517/tam3517.h
> @@ -0,0 +1,388 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _TAM3517_H_
> +#define _TAM3517_H_
> +
> +const omap3_sysinfo sysinfo = {
> + DDR_DISCRETE,
> + "TAM3517 Twister Board",
> + "NAND",
> +};
> +
> +/*
> + * IEN - Input Enable
> + * IDIS - Input Disable
> + * PTD - Pull type Down
> + * PTU - Pull type Up
> + * DIS - Pull type selection is inactive
> + * EN - Pull type selection is active
> + * M0 - Mode 0
> + * The commented string gives the final mux configuration for that pin
> + */
> +#define MUX_TAM3517() \
> + /* SDRC */\
> + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(SDRC_CKE0), (M0)) \
> + MUX_VAL(CP(SDRC_CKE1), (M0)) \
> + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
> + /* GPMC */\
> + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
> + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
> + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
> + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
> + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
> + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
> + /* DSS */\
> + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
> + /* CAMERA */\
> + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
> + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
> + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
> + /* MMC */\
> + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
> + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
> + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
> + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
> + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
> + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4))/*CardDetect*/\
> + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
> + \
> + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
> + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
> + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
> + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
> + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
> + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
> + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
> + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
> + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
> + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
> + /* McBSP */\
> + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
> + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
> + \
> + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
> + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
> + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
> + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
> + \
> + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
> + \
> + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
> + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
> + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
> + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
> + /* UART */\
> + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
> + MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
> + \
> + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
> + \
> + MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
> + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
> + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
> + /* I2C */\
> + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
> + /* McSPI */\
> + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
> + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
> + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
> + \
> + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
> + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
> + /* CCDC */\
> + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
> + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
> + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
> + /* RMII */\
> + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
> + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
> + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
> + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
> + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
> + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
> + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
> + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
> + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
> + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
> + /* HECC */\
> + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
> + /* HSUSB */\
> + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M4)) \
> + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
> + /* HDQ */\
> + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
> + /* Control and debug */\
> + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) /*SYS_nRESWARM */\
> + /* - GPIO30 */\
> + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
> + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
> + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
> + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
> + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
> + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
> + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
> + /* - VIO_1V8*/\
> + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
> + \
> + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
> + /* JTAG */\
> + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
> + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
> + /* ETK (ES2 onwards) */\
> + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
> + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
> + /* Die to Die */\
> + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
> + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
> + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index c83d861..343e82f 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -188,6 +188,7 @@ dig297 arm armv7 dig297 comelit
> omap3_zoom1 arm armv7 zoom1 logicpd omap3
> omap3_zoom2 arm armv7 zoom2 logicpd omap3
> omap3_mvblx arm armv7 mvblx matrix_vision omap3
> +tam3517 arm armv7 tam3517 technexion omap3
> omap3_beagle arm armv7 beagle ti omap3
> omap3_evm arm armv7 evm ti omap3
> omap3_evm_quick_mmc arm armv7 evm ti omap3
> diff --git a/include/configs/tam3517.h b/include/configs/tam3517.h
> new file mode 100644
> index 0000000..94a7600
> --- /dev/null
> +++ b/include/configs/tam3517.h
> @@ -0,0 +1,427 @@
> +/*
> + * Default configuration for TAM3517 boards.
> + *
> + * Maintainer: Tapani Utriainen <linuxfae at technexion.com>
> + *
> + * Copyright (C) 2009 TechNexion Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
> +#define CONFIG_OMAP 1 /* the Sitara is really a */
> +#define CONFIG_OMAP34XX 1 /* rebranded OMAP... */
> +#define CONFIG_TAM3517 1 /* working with TAM3517 */
> +
> +#define CONFIG_EMIF4 1 /* The chip has EMIF4 controller */
> +#define CONFIG_XR16L2751 1
Boolean CONFIG_* options should not have a value.
Please, fix globally.
> +
> +#include <asm/arch/cpu.h> /* get chip and board defs */
> +#include <asm/arch/omap3.h>
> +
> +/*
> + * Display CPU and Board information
> + */
> +#define CONFIG_DISPLAY_CPUINFO 1
> +#define CONFIG_DISPLAY_BOARDINFO 1
> +
> +/* Clock Defines */
> +#define V_OSCK 26000000 /* Clock output from T2 */
> +#define V_SCLK (V_OSCK >> 1)
> +
> +#undef CONFIG_USE_IRQ /* no support for IRQs */
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +#define CONFIG_REVISION_TAG 1
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1024 << 10))
> +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
> + /* initial data */
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x800
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
> + CONFIG_SYS_INIT_RAM_SIZE - \
> + GENERATED_GBL_DATA_SIZE)
> +
> +#if CONFIG_DRAM_BUS_WIDTH == 16
> +#define _CONFIG_DRAM_BUS_WIDTH "16"
> +#else
> +#ifndef CONFIG_DRAM_BUS_WIDTH
> +#define CONFIG_DRAM_BUS_WIDTH 32
> +#endif
> +#define _CONFIG_DRAM_BUS_WIDTH "32"
> +#endif
> +#if CONFIG_DRAM_SIZE == 128
> +#define _CONFIG_DRAM_SIZE "128"
> +#elif CONFIG_DRAM_SIZE == 64
> +#define _CONFIG_DRAM_SIZE "64"
> +#else
> +#ifndef CONFIG_DRAM_SIZE
> +#define CONFIG_DRAM_SIZE 256
> +#endif
> +#define _CONFIG_DRAM_SIZE "256"
> +#endif
> +#if CONFIG_NAND_BUS_WIDTH == 8
> +#define _CONFIG_NAND_BUS_WIDTH "8"
> +#else
> +#ifndef CONFIG_NAND_BUS_WIDTH
> +#define CONFIG_NAND_BUS_WIDTH 16
> +#endif
> +#define _CONFIG_NAND_BUS_WIDTH "16"
> +#endif
> +
> +/*
> + * DDR related
> + */
> +#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
> +
> +#define CONFIG_SYS_CS0_SIZE (CONFIG_DRAM_SIZE * 1024 * 1024)
> +
> +/*
> + * Hardware drivers
> + */
> +
> +/*
> + * NS16550 Configuration
> + */
> +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
> +#define CONFIG_SERIAL1 1 /* UART1 on TAM3517 EVM */
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
> + 115200}
> +
> +#define CONFIG_MMC 1
> +#define CONFIG_GENERIC_MMC 1 /* Extra MMC commands */
> +#define CONFIG_OMAP_HSMMC 1
> +#define CONFIG_DOS_PARTITION 1
> +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
> +
> +/* USB
> + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
> + * Enable CONFIG_MUSB_UDD for Device functionalities.
> + */
> +#define CONFIG_USB_AM35X 1
> +#define CONFIG_MUSB_HCD 1
> +/*#define CONFIG_MUSB_UDC 1*/
> +
> +#ifdef CONFIG_USB_AM3517
> +
> +#ifdef CONFIG_MUSB_HCD
> +#define CONFIG_CMD_USB
> +
> +#define CONFIG_USB_STORAGE
> +#define CONGIG_CMD_STORAGE
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
> +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
> +
> +#ifdef CONFIG_USB_KEYBOARD
> +#define CONFIG_SYS_USB_EVENT_POLL
> +#define CONFIG_PREBOOT "usb start"
> +#endif /* CONFIG_USB_KEYBOARD */
> +
> +#endif /* CONFIG_MUSB_HCD */
> +
> +#ifdef CONFIG_MUSB_UDC
> +/* USB device configuration */
> +#define CONFIG_USB_DEVICE 1
> +#define CONFIG_USB_TTY 1
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
> +/* Change these to suit your needs */
> +#define CONFIG_USBD_VENDORID 0x0451
> +#define CONFIG_USBD_PRODUCTID 0x5678
> +#define CONFIG_USBD_MANUFACTURER "TechNexion Ltd."
> +#define CONFIG_USBD_PRODUCT_NAME "TAM3517"
> +#endif /* CONFIG_MUSB_UDC */
> +
> +#endif /* CONFIG_USB_AM3517 */
> +
> +#ifdef CONFIG_BOOT_FROM_MMC
> +#define CONFIG_ENV_IS_NOWHERE 1
> +#else
> +#define CONFIG_ENV_IS_IN_NAND 1
> +#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
> +
> +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
> +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
> +#define CONFIG_ENV_ADDR CONFIG_ENV_ADDR
> +#endif
> +
> +/* commands to include */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_EXT2 /* EXT2 Support */
> +#define CONFIG_CMD_FAT /* FAT support */
> +#define CONFIG_CMD_EEPROM
> +
> +
> +#define CONFIG_CMD_I2C /* I2C serial bus support */
> +#define CONFIG_CMD_MMC /* MMC support */
> +#define CONFIG_CMD_NAND /* NAND support */
> +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
> +#undef CONFIG_CMD_FPGA /* No FPGA configuration Support*/
> +#undef CONFIG_CMD_IMI /* iminfo */
> +#undef CONFIG_CMD_IMLS /* List all found images */
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_HARD_I2C 1
> +#define CONFIG_SYS_I2C_SPEED 400000
> +#define CONFIG_SYS_I2C_SLAVE 1
> +#define CONFIG_SYS_I2C_BUS 0
> +#define CONFIG_SYS_I2C_BUS_SELECT 1
> +#undef CONFIG_I2C_MULTI_BUS
> +#define CONFIG_DRIVER_OMAP34XX_I2C 1
> +
> +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 ms */
> +
> +#ifndef CONFIG_CMD_NET
> +#define CONFIG_CMD_NET 1
> +#endif
> +
> +/*
> + * Board NAND Info.
> + */
> +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
> + /* to access nand */
> +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
> + /* to access */
> + /* nand at CS0 */
> +
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
> + /* NAND devices */
> +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
> +
> +/* Environment information */
> +#define CONFIG_BOOTFILE "uImage"
> +#define CONFIG_BOOTDELAY 1
> +
> +/*
> + For LG 4.3" panel use
> + "panel-generic.disp_timings=8000,480/8/4/41,272/4/2/10,24\0" \
> +*/
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "loadaddr=0x82000000\0" \
> + "console=ttyO0,115200n8\0" \
> + "mpurate=600\0" \
> + "video_mode=vram=6M omapfb.vram=0:2M,1:2M,2:2M omapdss.def_disp=lcd "\
> + "panel-generic.disp_timings=33300,800/210/46/1,480/22/23/1,24"\
> + "\0"\
> + "mmcdev=0\0" \
> + "mmcroot=/dev/mmcblk0p2 rw\0" \
> + "mmcrootfstype=ext3 rootwait\0" \
> + "nandroot=ubi0:rootfs ubi.mtd=4\0" \
> + "nandrootfstype=ubifs\0" \
> + "mmcargs=setenv bootargs console=${console} " \
> + "mpurate=${mpurate} " \
> + "${video_mode} " \
> + "${extra_options} " \
> + "root=${mmcroot} " \
> + "rootfstype=${mmcrootfstype}\0" \
> + "nandargs=setenv bootargs console=${console} " \
> + "mpurate=${mpurate} " \
> + "${video_mode} " \
> + "${extra_options} " \
> + "root=${nandroot} " \
> + "rootfstype=${nandrootfstype}\0" \
> + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source ${loadaddr}\0" \
> + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "bootm ${loadaddr}\0" \
> + "nandboot=echo Booting from nand ...; " \
> + "run nandargs; " \
> + "nand read ${loadaddr} 280000 400000; " \
> + "bootm ${loadaddr}\0" \
> +
> +#define CONFIG_BOOTCOMMAND \
> + "if mmc rescan ${mmcdev}; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loaduimage; then " \
> + "run mmcboot; " \
> + "else run nandboot; " \
> + "fi; " \
> + "fi; " \
> + "else run nandboot; fi"
> +
> +
> +/* turn on command-line edit/hist/auto */
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_COMMAND_HISTORY
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_AUTOCOMPLETE
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define V_PROMPT "TAM3517 # "
> +
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_PROMPT V_PROMPT
> +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
> +#define CONFIG_CMD_RUN
> +
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 64 /* max number of command */
> + /* args */
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
> +/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
> +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> + 0x01F00000) /* 31MB */
> +
> +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
> + /* address */
> +#define CONFIG_SYS_TEXT_BASE 0x80008000
> +/*
> + * AM3517 has 12 GP timers, they can be driven by the system clock
> + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> + * This rate is divided by a local divisor.
> + */
> +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
> +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
> +#define CONFIG_SYS_HZ 1000
> +
> +/*-----------------------------------------------------------------------
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
> +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
> +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
> +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
> +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
> +
> +/* SDRAM Bank Allocation method */
> +#define SDRC_R_B_C 1
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +
> +/* **** PISMO SUPPORT *** */
> +
> +/* Configure the PISMO */
> +#define PISMO1_NAND_SIZE GPMC_SIZE_128M
> +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
> +
> +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
> + /* on one chip */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
> +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
> +
> +#define CONFIG_SYS_FLASH_BASE boot_flash_base
> +
> +/* Monitor at start of flash */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> +
> +#define CONFIG_NAND_OMAP_GPMC
> +#if CONFIG_NAND_BUS_WIDTH == 16
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
> +#else
> +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * CFI FLASH driver setup
> + */
> +/* timeout values are in ticks */
> +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
> +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
> +
> +/* Flash banks JFFS2 should use */
> +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
> + CONFIG_SYS_MAX_NAND_DEVICE)
> +
> +
> +/*-----------------------------------------------------
> + * ethernet support for TAM3517
> + *-----------------------------------------------------
> + */
> +#define CONFIG_MII
> +
> +#if defined(CONFIG_CMD_NET)
> +/* Disable u-boot support for EMAC LAN, due compile problems
> + Linux kernel support is enough to enable the interface
> +*/
There are some patches on the list that should fix U-Boot
issues with davinci EMAC, so probably you should wait for
them to get in.
Otherwise, multiline comment is in wrong format.
> +/*
> +#define CONFIG_DRIVER_TI_EMAC
> +#define CONFIG_DRIVER_TI_EMAC_USE_RMII
> +#define CONFIG_EMAC_MDIO_PHY_NUM 0
> +#define CONFIG_ARM926EJS 1
> +*/
> +#define CONFIG_NET_RETRY_COUNT 10
> +#define CONFIG_NET_MULTI
> +
> +#define CONFIG_SMC911X 1
> +#define CONFIG_SMC911X_16_BIT 1
> +#define CONFIG_SMC911X_BASE 0x2C000000
> +#define CONFIG_SMC911X_NO_EEPROM 1
Use tabs for alignment, please, fix globally.
> +
> +#endif
> +
> +#endif /* __CONFIG_H */
>
> --
> 1.7.6
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
Regards,
Igor.
More information about the U-Boot
mailing list