[U-Boot] [PATCH] powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support

Andy Fleming afleming at gmail.com
Tue Apr 24 20:35:17 CEST 2012


On Thu, Mar 15, 2012 at 1:41 AM, Prabhakar Kushwaha
<prabhakar at freescale.com> wrote:
>  - BSC9131 is integrated device that targets Femto base station market.
>   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
>   technologies with MAPLE-B2F baseband acceleration processing elements.
>  - BSC9130 is exactly same as BSC9131 except that the max e500v2
>   core and DSP core frequencies are 800M(these are 1G in case of 9131).
>  - BSC9231 is similar to BSC9131 except no MAPLE
>
> The BSC9131 SoC includes the following function and features:
>    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
>      L2 cache
>    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
>    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
>      Processing (MAPLE-B2F)
>    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
>     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
>     and CRC algorithms
>    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
>     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
>     operations
>    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
>     ECC, up to 400-MHz clock/800 MHz data rate
>    . Dedicated security engine featuring trusted boot
>    . DMA controller
>    . OCNDMA with four bidirectional channels
>    . Interfaces
>    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
>      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
>    . eTSEC 1 supports RGMII/RMII
>    . eTSEC 2 supports RGMII
>    . High-speed USB 2.0 host and device controller with ULPI interface
>    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
>    . Antenna interface controller (AIC), supporting three industry standard
>      JESD207/three custom ADI RF interfaces (two dual port and one single port)
>      and three MAXIM's MaxPHY serial interfaces
>    . ADI lanes support both full duplex FDD support and half duplex TDD support
>    . Universal Subscriber Identity Module (USIM) interface that facilitates
>      communication to SIM cards or Eurochip pre-paid phone cards
>    . TDM with one TDM port
>    . Two DUART, four eSPI, and two I2C controllers
>    . Integrated Flash memory controller (IFC)
>    . TDM with 256 channels
>    . GPIO
>    . Sixteen 32-bit timers
>
> The DSP portion of the SoC consists of DSP core (SC3850) and various
> accelerators pertaining to DSP operations.
>
> This patch takes care of code pertaining to power side functionality only.
>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh at freescale.com>
> Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
> Signed-off-by: Akhil Goyal <Akhil.Goyal at freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
> Signed-off-by: Rajan Srivastava <rajan.srivastava at freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> ---
> Note: Name of PSC9131 has been changed to BSC9131 because of new nomenclature.
>      So please reject earlier patch:
>        "PSC9131/PSC9130/PSC9231 Processor Support Added"
>               http://patchwork.ozlabs.org/patch/141048/
>
>  arch/powerpc/cpu/mpc85xx/Makefile         |    1 +
>  arch/powerpc/cpu/mpc8xxx/cpu.c            |    6 +-
>  arch/powerpc/include/asm/config_mpc85xx.h |   14 +++-
>  arch/powerpc/include/asm/immap_85xx.h     |  117 ++++++++++++++++++++++++++++-
>  arch/powerpc/include/asm/processor.h      |    5 +
>  5 files changed, 140 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
> index 058d609..e3a7c14 100644
> --- a/arch/powerpc/cpu/mpc85xx/Makefile
> +++ b/arch/powerpc/cpu/mpc85xx/Makefile
> @@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041)     += ddr-gen3.o
>  COBJS-$(CONFIG_PPC_P3060)      += ddr-gen3.o
>  COBJS-$(CONFIG_PPC_P4080)      += ddr-gen3.o
>  COBJS-$(CONFIG_PPC_P5020)      += ddr-gen3.o
> +COBJS-$(CONFIG_BSC9131)                += ddr-gen3.o
>
>  COBJS-$(CONFIG_CPM2)   += ether_fcc.o
>  COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
> diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
> index 0365ca8..7340f69 100644
> --- a/arch/powerpc/cpu/mpc8xxx/cpu.c
> +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright 2009-2011 Freescale Semiconductor, Inc.
> + * Copyright 2009-2012 Freescale Semiconductor, Inc.
>  *
>  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
>  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
> @@ -113,6 +113,10 @@ struct cpu_type cpu_type_list [] = {
>        CPU_TYPE_ENTRY(P5010, P5010_E, 1),
>        CPU_TYPE_ENTRY(P5020, P5020, 2),
>        CPU_TYPE_ENTRY(P5020, P5020_E, 2),
> +       CPU_TYPE_ENTRY(BSC9130, 9130, 1),
> +       CPU_TYPE_ENTRY(BSC9130, 9130_E, 1),
> +       CPU_TYPE_ENTRY(BSC9131, 9131, 1),
> +       CPU_TYPE_ENTRY(BSC9131, 9131_E, 1),
>  #elif defined(CONFIG_MPC86xx)
>        CPU_TYPE_ENTRY(8610, 8610, 1),
>        CPU_TYPE_ENTRY(8641, 8641, 2),
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
> index 8654625..d1b9d5b 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011-2012 Freescale Semiconductor, Inc.
>  *
>  * This program is free software; you can redistribute it and/or
>  * modify it under the terms of the GNU General Public License as
> @@ -459,6 +459,18 @@
>  #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
>  #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
>
> +#elif defined(CONFIG_BSC9131)
> +#define CONFIG_MAX_CPUS                        1
> +#define CONFIG_FSL_SDHC_V2_3
> +#define CONFIG_SYS_FSL_NUM_LAWS                12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT      4
> +#define CONFIG_NUM_DDR_CONTROLLERS     1
> +#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
> +#define CONFIG_NAND_FSL_IFC
> +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +
>  #else
>  #error Processor type not defined for this platform
>  #endif
> diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
> index 9b08cb8..9e52705 100644
> --- a/arch/powerpc/include/asm/immap_85xx.h
> +++ b/arch/powerpc/include/asm/immap_85xx.h
> @@ -1,7 +1,7 @@
>  /*
>  * MPC85xx Internal Memory Map
>  *
> - * Copyright 2007-2011 Freescale Semiconductor, Inc.
> + * Copyright 2007-2012 Freescale Semiconductor, Inc.
>  *
>  * Copyright(c) 2002,2003 Motorola Inc.
>  * Xianghua Xiao (x.xiao at motorola.com)
> @@ -1870,7 +1870,11 @@ typedef struct ccsr_gur {
>  #define MPC85xx_PORPLLSR_DDR_RATIO     0x3e000000
>  #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       25
>  #else
> +#ifdef CONFIG_BSC9131
> +#define MPC85xx_PORPLLSR_DDR_RATIO     0x00003f00
> +#else
>  #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003e00
> +#endif


Do we have an understanding of why this changed? The definition of
these fields is beginning to get arbitrarily complicated.


>  #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       9
>  #endif
>  #define MPC85xx_PORPLLSR_QE_RATIO      0x3e000000
> @@ -2017,6 +2021,50 @@ typedef struct ccsr_gur {
>  #define MPC85xx_PMUXCR_SPI_MASK                0x00600000
>  #define MPC85xx_PMUXCR_SPI             0x00000000
>  #endif
> +#if defined(CONFIG_BSC9131)
> +#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ      0x40000000
> +#define MPC85xx_PMUXCR_TSEC2_USB               0xC0000000
> +#define MPC85xx_PMUXCR_TSEC2_1588_PPS          0x10000000
> +#define MPC85xx_PMUXCR_TSEC2_1588_RSVD         0x30000000
> +#define MPC85xx_PMUXCR_IFC_AD_GPIO             0x04000000
> +#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK                0x0C000000
> +#define MPC85xx_PMUXCR_IFC_AD15_GPIO           0x01000000
> +#define MPC85xx_PMUXCR_IFC_AD15_TIMER2         0x02000000
> +#define MPC85xx_PMUXCR_IFC_AD16_GPO8           0x00400000
> +#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0                0x00800000
> +#define MPC85xx_PMUXCR_IFC_AD17_GPO            0x00100000
> +#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK       0x00300000
> +#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP     0x00200000
> +#define MPC85xx_PMUXCR_IFC_CS2_GPO65           0x00040000
> +#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI         0x00080000
> +#define MPC85xx_PMUXCR_SDHC_USIM               0x00010000
> +#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK                0x00020000
> +#define MPC85xx_PMUXCR_SDHC_GPIO77             0x00030000
> +#define MPC85xx_PMUXCR_SDHC_RESV               0x00004000
> +#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD                0x00008000
> +#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4                0x0000C000
> +#define MPC85xx_PMUXCR_USB_CLK_UART_SIN                0x00001000
> +#define MPC85xx_PMUXCR_USB_CLK_GPIO69          0x00002000
> +#define MPC85xx_PMUXCR_USB_CLK_TIMER3          0x00003000
> +#define MPC85xx_PMUXCR_USB_UART_GPIO0          0x00000400
> +#define MPC85xx_PMUXCR_USB_RSVD                        0x00000C00
> +#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN      0x00000800
> +#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL   0x00000100
> +#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72      0x00000200
> +#define MPC85xx_PMUXCR_USB_D1_2_RSVD           0x00000300
> +#define MPC85xx_PMUXCR_USB_DIR_GPIO2           0x00000040
> +#define MPC85xx_PMUXCR_USB_DIR_TIMER1          0x00000080
> +#define MPC85xx_PMUXCR_USB_DIR_MCP_B           0x000000C0
> +#define MPC85xx_PMUXCR_SPI1_UART3              0x00000010
> +#define MPC85xx_PMUXCR_SPI1_SIM                        0x00000020
> +#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74     0x00000030
> +#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B    0x00000004
> +#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen  0x00000008
> +#define MPC85xx_PMUXCR_SPI1_CS2_GPO75          0x0000000C
> +#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM   0x00000001
> +#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen  0x00000002
> +#define MPC85xx_PMUXCR_SPI1_CS3_GPO76          0x00000003
> +#endif
>        u32     pmuxcr2;        /* Alt. function signal multiplex control 2 */
>  #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
>  #define MPC85xx_PMUXCR2_UART_GPIO              0x40000000
> @@ -2047,7 +2095,69 @@ typedef struct ccsr_gur {
>  #define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f8000
>  #define MPC85xx_PMUXCR2_USB            0x00150000
>  #endif
> +#if defined(CONFIG_BSC9131)
> +#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD             0X40000000
> +#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS            0X80000000
> +#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42             0xC0000000
> +#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2               0x10000000
> +#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK            0x20000000
> +#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43             0x30000000
> +#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD             0x04000000
> +#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B           0x08000000
> +#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44             0x0C000000
> +#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED            0x01000000
> +#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD               0x02000000
> +#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45             0x03000000
> +#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP                        0x00400000
> +#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B            0x00800000
> +#define MPC85xx_PMUXCR2_ANT1_TIMER5                    0x00100000
> +#define MPC85xx_PMUXCR2_ANT1_TSEC_1588                 0x00200000
> +#define MPC85xx_PMUXCR2_ANT1_GPIO95_19                 0x00300000
> +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK     0x00040000
> +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD          0x00080000
> +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20     0x000C0000
> +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0           0x00010000
> +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3          0x00020000
> +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84          0x00030000
> +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4               0x00004000
> +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7         0x00008000
> +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88          0x0000C000
> +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK                0x00001000
> +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9         0x00002000
> +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22          0x00003000
> +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7         0x00000400
> +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11     0x00000800
> +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24                0x00000C00
> +#define MPC85xx_PMUXCR2_ANT2_RSVD                      0x00000100
> +#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA              0x00000300
> +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB                0x00000040
> +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO       0x000000C0
> +#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD                        0x00000010
> +#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8              0x00000020
> +#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61              0x00000030
> +#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53                 0x00000004
> +#define MPC85xx_PMUXCR2_ANT3_DO_TDM                    0x00000001
> +#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49              0x00000002
> +       u32     pmuxcr3;
> +
> +#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM                 0x40000000
> +#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51          0x80000000
> +#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B    0x10000000
> +#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53          0x20000000
> +#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B                 0x04000000
> +#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54                        0x08000000
> +#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT       0x01000000
> +#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56          0x02000000
> +#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT              0x00400000
> +#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57               0x00800000
> +#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93                 0x00100000
> +#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94                 0x00040000
> +#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD                  0x00010000
> +#define MPC85xx_PMUXCR3_ANT2_GPO89                     0x00030000
> +       u32 pmuxcr4;
> +#else
>        u8      res6[8];
> +#endif
>        u32     devdisr;        /* Device disable control */
>  #define MPC85xx_DEVDISR_PCI1           0x80000000
>  #define MPC85xx_DEVDISR_PCI2           0x40000000
> @@ -2533,4 +2643,9 @@ struct ccsr_rman {
>  #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
>  #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
>
> +#if defined(CONFIG_BSC9131)
> +#define HALTED_TO_HALT_REQ_MASK_REG    0xff7e0e30
> +#define HALTED_TO_HALT_REQ_MASK_0      0x80000000
> +#endif


Why not just add this register to the ccsr_gur struct? If someone
attempts to adopt this code, and changes the CCSR, this hard-coded
address will break.

Andy


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