[U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines

[Thierry Reding]

The MMC core sometimes reads buffers that are smaller than a complete
cacheline, for example when reading the SCR. In order to avoid a warning
from the ARM v7 cache handling code, this patch makes sure that complete
cachelines are flushed.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 drivers/mmc/tegra2_mmc.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c
index fb8a57d..3615876 100644
--- a/drivers/mmc/tegra2_mmc.c
+++ b/drivers/mmc/tegra2_mmc.c
@@ -323,12 +323,13 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		}
 		writel(mask, &host->reg->norintsts);
 		if (data->flags & MMC_DATA_READ) {
+			ulong end = (ulong)data->dest +
+				roundup(data->blocks * data->blocksize,
+						ARCH_DMA_MINALIGN);
 			if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1))
 				printf("Warning: unaligned read from %p "
 					"may fail\n", data->dest);
-			invalidate_dcache_range((ulong)data->dest,
-				(ulong)data->dest +
-					data->blocks * data->blocksize);
+			invalidate_dcache_range((ulong)data->dest, end);
 		}
 	}
 
-- 
1.7.10