[U-Boot] [PATCH v2 2/2] EXYNOS4: Add ORIGEN_QUAD board support
Minkyu Kang
mk7.kang at samsung.com
Sat Dec 15 06:56:26 CET 2012
Dear Jeong-Hyeon Kim,
On 13/12/12 19:37, Jeong-Hyeon Kim wrote:
> ORIGEN_QUAD board is based on Samsung's Exynos4412 SoC.
>
> Signed-off-by: Jeong-Hyeon Kim <jhkim at insignal.co.kr>
> ---
> Makefile | 2 +-
> board/samsung/origen_quad/Makefile | 59 ++++++
> board/samsung/origen_quad/boot.c | 72 +++++++
> board/samsung/origen_quad/clock.c | 103 ++++++++++
> board/samsung/origen_quad/dmc.c | 163 ++++++++++++++++
> board/samsung/origen_quad/lowlevel_init.S | 151 +++++++++++++++
> board/samsung/origen_quad/origen_quad.c | 163 ++++++++++++++++
> board/samsung/origen_quad/setup.h | 300 +++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/origen_quad.h | 179 +++++++++++++++++
> tools/Makefile | 2 +
> 11 files changed, 1194 insertions(+), 1 deletion(-)
> create mode 100644 board/samsung/origen_quad/Makefile
> create mode 100644 board/samsung/origen_quad/boot.c
> create mode 100644 board/samsung/origen_quad/clock.c
> create mode 100644 board/samsung/origen_quad/dmc.c
> create mode 100644 board/samsung/origen_quad/lowlevel_init.S
> create mode 100644 board/samsung/origen_quad/origen_quad.c
> create mode 100644 board/samsung/origen_quad/setup.h
> create mode 100644 include/configs/origen_quad.h
missing MAINTAINER entry.
>
> +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
> diff --git a/board/samsung/origen_quad/clock.c b/board/samsung/origen_quad/clock.c
> new file mode 100644
> index 0000000..7570039
> --- /dev/null
> +++ b/board/samsung/origen_quad/clock.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics
> + *
> + * Copyright (C) 2012 Insignal
> + *
> + * Clock setup for the Insignal OrigenQUAD board (Exynos4x12)
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/clock.h>
> +#include "setup.h"
> +
> +void clock_ctrl_init(void)
> +{
> + struct exynos4x12_clock *clk =
> + (struct exynos4x12_clock *)EXYNOS4_CLOCK_BASE;
please use samsung_get_base_clock() function.
> +
> + /* CLK_SRC_CPU */
> + writel(0x00000000, &clk->src_cpu);
> + sdelay(0x10000);
> +
> + /* CLK_DIV_DMC */
> + writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
> + writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
> +
> + /* CLK_SRC_TOP */
> + writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
> + writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
> + sdelay(0x10000);
> + writel(CLK_DIV_TOP_VAL, &clk->div_top);
> +
> + /* LEFTBUS */
> + writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
> + sdelay(0x10000);
> + writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
> + /* RIGHTBUS */
> + writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
> + sdelay(0x10000);
> + writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
> +
> + /* PLL locktime */
> + writel(APLL_LOCK_VAL, &clk->apll_lock);
> + writel(MPLL_LOCK_VAL, &clk->mpll_lock);
> + writel(EPLL_LOCK_VAL, &clk->epll_lock);
> + writel(VPLL_LOCK_VAL, &clk->vpll_lock);
> +
> + /* CLK_DIV_CPU0/1 */
> + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
> + writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
> +
> + /* APLL */
> + writel(APLL_CON1_VAL, &clk->apll_con1);
> + writel(APLL_CON0_VAL, &clk->apll_con0);
> + /* MPLL */
> + writel(MPLL_CON1_VAL, &clk->mpll_con1);
> + writel(MPLL_CON0_VAL, &clk->mpll_con0);
> + /* EPLL */
> + writel(EPLL_CON2_VAL, &clk->epll_con2);
> + writel(EPLL_CON1_VAL, &clk->epll_con1);
> + writel(EPLL_CON0_VAL, &clk->epll_con0);
> + /* VPLL */
> + writel(VPLL_CON2_VAL, &clk->vpll_con2);
> + writel(VPLL_CON1_VAL, &clk->vpll_con1);
> + writel(VPLL_CON0_VAL, &clk->vpll_con0);
> + sdelay(0x40000);
> +
> + writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
> + writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
> + writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
> + writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
> + sdelay(0x10000);
> +
> + /* UART */
> + writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
> + writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
> +
> + /* for IROM */
> + /* CLK_DIV_FSYS2 */
> + writel(0x0000000F, &clk->div_fsys2); /* MMC2 - SDMMC */
> + /* CLK_DIV_FSYS3 */
> + writel(0x00000100, &clk->div_fsys3); /* MMC4 - eMMC */
magic values?
> +}
> +
> diff --git a/board/samsung/origen_quad/dmc.c b/board/samsung/origen_quad/dmc.c
> new file mode 100644
> index 0000000..0bb1164
> --- /dev/null
> +++ b/board/samsung/origen_quad/dmc.c
> @@ -0,0 +1,163 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics
> + *
> + * Copyright (C) 2012 Insignal
> + *
> + * Memory setup for the Insignal OrigenQUAD board (Exynos4x12)
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/io.h>
> +#include <asm/arch/dmc.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cpu.h>
> +#include "setup.h"
> +
> +void mem_ctrl_init(void)
> +{
> + struct exynos4_clock *clk =
> + (struct exynos4_clock *)EXYNOS4_CLOCK_BASE;
> + struct exynos4_dmc *dmc0 =
> + (struct exynos4_dmc *)(EXYNOS4_MIU_BASE);
> + struct exynos4_dmc *dmc1 =
> + (struct exynos4_dmc *)(EXYNOS4_MIU_BASE + 0x10000);
> +
> + /* Set DMC to 50MHz for IROM */
> + writel(0x00117713, &clk->div_dmc0);
Already set at clock_ctrl_init?
> +
> + /*
> + * DMC 0
> + */
> + writel(0xE3855403, &dmc0->phyzqcontrol);
> + writel(0x71101008, &dmc0->phycontrol0);
> + writel(0x7110100A, &dmc0->phycontrol0);
> + writel(0x00000084, &dmc0->phycontrol1);
> + writel(0x71101008, &dmc0->phycontrol0);
> + writel(0x0000008C, &dmc0->phycontrol1);
> + writel(0x00000084, &dmc0->phycontrol1);
> + writel(0x0000008C, &dmc0->phycontrol1);
> + writel(0x00000084, &dmc0->phycontrol1);
> + writel(0x0FFF30CA, &dmc0->concontrol);
> + writel(0x00202500, &dmc0->memcontrol);
> + writel(0x40C01323, &dmc0->memconfig0);
> + writel(0x80000007, &dmc0->ivcontrol);
> +
> + writel(0x64000000, &dmc0->prechconfig);
> + writel(0x9C4000FF, &dmc0->phycontrol0);
> + writel(0x0000005D, &dmc0->timingref);
> +
> +#if (CONFIG_CLK_MPLL == 330)
> + writel(0x2b47654e, &dmc0->timingrow);
> + writel(0x35330306, &dmc0->timingdata);
> + writel(0x442f0365, &dmc0->timingpower);
> +#else
> + writel(0x34498691, &dmc0->timingrow);
> + writel(0x36330306, &dmc0->timingdata);
> + writel(0x50380365, &dmc0->timingpower);
> +#endif
> + sdelay(0x100000);
> +
> + writel(0x07000000, &dmc0->directcmd);
> + sdelay(0x100000);
> +
> + writel(0x00071C00, &dmc0->directcmd);
> + sdelay(0x100000);
> +
> + writel(0x00010BFC, &dmc0->directcmd);
> + sdelay(0x100000);
> +
> + writel(0x00000608, &dmc0->directcmd);
> + writel(0x00000810, &dmc0->directcmd);
> + writel(0x00000C08, &dmc0->directcmd);
> +
> + /*
> + * DMC 1
> + */
> + writel(0xE3855403, &dmc1->phyzqcontrol);
> + writel(0x71101008, &dmc1->phycontrol0);
> + writel(0x7110100A, &dmc1->phycontrol0);
> + writel(0x00000084, &dmc1->phycontrol1);
> + writel(0x71101008, &dmc1->phycontrol0);
> + writel(0x0000008C, &dmc1->phycontrol1);
> + writel(0x00000084, &dmc1->phycontrol1);
> + writel(0x0000008C, &dmc1->phycontrol1);
> + writel(0x00000084, &dmc1->phycontrol1);
> + writel(0x0FFF30CA, &dmc1->concontrol);
> + writel(0x00202500, &dmc1->memcontrol);
> + writel(0x40C01323, &dmc1->memconfig0);
> + writel(0x80000007, &dmc1->ivcontrol);
> + writel(0x64000000, &dmc1->prechconfig);
> + writel(0x9C4000FF, &dmc1->phycontrol0);
> + writel(0x0000005D, &dmc1->timingref);
> +
> +#if (CONFIG_CLK_MPLL == 330)
> + writel(0x2b47654e, &dmc1->timingrow);
> + writel(0x35330306, &dmc1->timingdata);
> + writel(0x442f0365, &dmc1->timingpower);
> +#else
> + writel(0x34498691, &dmc1->timingrow);
> + writel(0x36330306, &dmc1->timingdata);
> + writel(0x50380365, &dmc1->timingpower);
> +#endif
> + sdelay(0x100000);
> +
> + writel(0x07000000, &dmc1->directcmd);
> + sdelay(0x100000);
> +
> + writel(0x00071C00, &dmc1->directcmd);
> + sdelay(0x100000);
> +
> + writel(0x00010BFC, &dmc1->directcmd);
> + sdelay(0x100000);
> +
> + writel(0x00000608, &dmc1->directcmd);
> + writel(0x00000810, &dmc1->directcmd);
> + writel(0x00000C08, &dmc1->directcmd);
> +}
> +
> +void mem_ctrl_init_2nd(void)
> +{
> + struct exynos4_dmc *dmc0 =
> + (struct exynos4_dmc *)(EXYNOS4_MIU_BASE);
> + struct exynos4_dmc *dmc1 =
> + (struct exynos4_dmc *)(EXYNOS4_MIU_BASE + 0x10000);
> +
> + writel(0x7F10100A, &dmc0->phycontrol0);
> + writel(0xE0000084, &dmc0->phycontrol1);
> + writel(0x7F10100B, &dmc0->phycontrol0);
> + sdelay(20000);
> + writel(0x0000008C, &dmc0->phycontrol1);
> + writel(0x00000084, &dmc0->phycontrol1);
> + sdelay(20000);
> +
> + writel(0x7F10100A, &dmc1->phycontrol0);
> + writel(0xE0000084, &dmc1->phycontrol1);
> + writel(0x7F10100B, &dmc1->phycontrol0);
> + sdelay(20000);
> + writel(0x0000008C, &dmc1->phycontrol1);
> + writel(0x00000084, &dmc1->phycontrol1);
> + sdelay(20000);
> +
> + writel(0x0FFF30FA, &dmc0->concontrol);
> + writel(0x0FFF30FA, &dmc1->concontrol);
> + writel(0x00202533, &dmc0->memcontrol);
> + writel(0x00202533, &dmc1->memcontrol);
There are too many magic values on this file.
Please fix it.
> +}
> diff --git a/board/samsung/origen_quad/origen_quad.c b/board/samsung/origen_quad/origen_quad.c
> new file mode 100644
> index 0000000..583fab0
> --- /dev/null
> +++ b/board/samsung/origen_quad/origen_quad.c
> @@ -0,0 +1,163 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics
> + *
> + * Copyright (C) 2012 Insignal
> + *
> + * Board initialize for the Insignal OrigenQUAD board (Exynos4x12)
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <netdev.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mmc.h>
> +#include <asm/arch/pinmux.h>
> +#include <asm/arch/power.h>
> +#include <asm/arch/clock.h>
> +#include "setup.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> + printf("\nBoard: " CONFIG_BOARDNAME "\n");
> + return 0;
> +}
> +#endif
> +
please remove this blank space.
> +
> +int board_init(void)
> +{
> +#ifdef CONFIG_EXYNOS_SPI
> + spi_init();
> +#endif
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
> + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
> + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
> + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
> +
> +#ifdef CONFIG_RESERVED_DRAM
> + gd->ram_size -= CONFIG_RESERVED_DRAM;
> +#endif
> +
> + return 0;
> +}
> +
> +void dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size =
> + get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> + gd->bd->bi_dram[1].size =
> + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
> + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> + gd->bd->bi_dram[2].size =
> + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE);
> + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> + gd->bd->bi_dram[3].size =
> + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
> +
> +#ifdef CONFIG_RESERVED_DRAM
> + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= CONFIG_RESERVED_DRAM;
> +#endif
> +}
> +
> +#ifdef CONFIG_GENERIC_MMC
> +int board_emmc_init(void)
> +{
> + int err;
blank line here.
> + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
> + if (err) {
> + debug("SDMMC0 not configured\n");
> + return err;
> + }
> + return s5p_mmc_init(0, 8);
> +}
> +
> +int board_sdmmc_init(void)
> +{
> + int err;
blank line here.
> + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
> + if (err) {
> + debug("SDMMC2 not configured\n");
> + return err;
> + }
> + return s5p_mmc_init(2, 4);
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int err;
> +
> + struct exynos4_power *power =
> + (struct exynos4_power *)samsung_get_base_power();
> +
> + if ((power->om_stat & 0x1E) == 0x8) {
what is 0x1E and 0x8?
> + err = board_emmc_init();
> + err = board_sdmmc_init();
> + } else {
> + err = board_sdmmc_init();
> + err = board_emmc_init();
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_SMC911X
> + if (smc9115_pre_init())
> + return -1;
> + return smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + return 0;
> +}
> +
> +static int board_uart_init(void)
> +{
> + int err;
blank line here.
> + err = exynos_pinmux_config(PERIPH_ID_UART, PINMUX_FLAG_NONE);
> + if (err)
> + debug("UART%d not configured\n",
> + PERIPH_ID_UART - PERIPH_ID_UART0);
> + return err;
> +}
> +
> +#ifdef CONFIG_BOARD_EARLY_INIT_F
> +int board_early_init_f(void)
> +{
> + int err;
> + err = board_uart_init();
> + if (err)
> + debug("UART%d init failed\n",
> + PERIPH_ID_UART - PERIPH_ID_UART0);
2 lines. then need brace this if statement.
> + return err;
> +}
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 388e4a4..66b9ee3 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -284,6 +284,7 @@ s5pc210_universal arm armv7 universal_c210 samsung
> smdk5250 arm armv7 smdk5250 samsung exynos
> smdkv310 arm armv7 smdkv310 samsung exynos
> trats arm armv7 trats samsung exynos
> +origen_quad arm armv7 origen_quad samsung exynos
It should be aligned with alphabetically.
> harmony arm armv7:arm720t harmony nvidia tegra20
> seaboard arm armv7:arm720t seaboard nvidia tegra20
> ventana arm armv7:arm720t ventana nvidia tegra20
> diff --git a/include/configs/origen_quad.h b/include/configs/origen_quad.h
> new file mode 100644
> index 0000000..d81eeb3
> --- /dev/null
> +++ b/include/configs/origen_quad.h
> @@ -0,0 +1,179 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics
> + *
> + * Copyright (C) 2012 Insignal
> + *
> + * Configuration settings for the Insignal OrigenQUAD board (Exynos4x12)
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_ORIGEN_QUAD_H
> +#define __CONFIG_ORIGEN_QUAD_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
> +#define CONFIG_S5P /* S5P Family */
> +#define CONFIG_EXYNOS4 /* which is in a Exynos4 series */
> +#define CONFIG_EXYNOS4412 /* which is in a Exynos4412 */
> +#define CONFIG_ORIGEN_QUAD /* which is in a ORIGEN QUAD */
> +#define CONFIG_BOARDNAME "Origen"
> +#define CONFIG_IDENT_STRING " for Insignal Origen"
> +#define CONFIG_MACH_TYPE 3455
Is it same board with Origen?
> +
> +#include <asm/arch/cpu.h> /* get chip and board defs */
> +
> +/*
> + * Clock / PLL
> + */
> +#define CONFIG_SYS_CLK_FREQ 24000000 /* 24MHz input clock */
> +#define CONFIG_CLK_APLL 1400
> +#define CONFIG_CLK_MPLL 400
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_PWM
> +
> +/*
> + * Memory
> + */
> +/* Default address */
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define CONFIG_SYS_TEXT_BASE 0x43E00000
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20UL))
> +/* Cache */
> +#define CONFIG_L2_OFF 1
> +#define CONFIG_SYS_DCACHE_OFF /* Keep L2 Cache Disabled */
> +/* DRAM */
> +#define CONFIG_NR_DRAM_BANKS 4 /* 256 MB * 4 = 1 GB */
> +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
> +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
> +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_2 (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
> +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_3 (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)
> +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_4 (PHYS_SDRAM_3 + PHYS_SDRAM_3_SIZE)
> +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
> +/* Reserved */
> +#define CONFIG_RESERVED_DRAM 0x100000
> +/* Mem test */
> +#define CONFIG_CMD_MEMORY
> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE - (8UL << 20UL))
> +
> +/*
> + * Serial
> + */
> +#define CONFIG_SERIAL2 2 /* use SERIAL2 in 0~3 */
> +#define CONFIG_SERIAL_MULTI 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * SD/MMC
> + */
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_MMC
> +#define CONFIG_SDHCI
> +#define CONFIG_S5P_SDHCI
> +#define CONFIG_CMD_MMC
> +
> +/*
> + * File System
> + */
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +
> +/*
> + * Flash
> + */
> +#define CONFIG_SYS_NO_FLASH
> +
> +/*
> + * Image map on sdmmc/emmc
> + */
> +#define CONFIG_SECURE_BL1_ONLY
> +#define CONFIG_SPL
> +#define CONFIG_MBR_SIZE (512)
> +#define CONFIG_SBL_SIZE (8UL << 10) /* 8KB */
> +#define CONFIG_BL1_SIZE (16UL << 10) /* 16KB */
> +#define CONFIG_BL2_SIZE (512UL << 10) /* 512KB */
> +
> +/*
> + * Console
> + */
> +#define CONFIG_SYS_PROMPT CONFIG_BOARDNAME " # "
> +/* Console I/O Buffer Size */
> +#define CONFIG_SYS_CBSIZE 256
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE 384
> +/* max number of command args */
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +
> +/*
> + * Commands
> + */
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_NET
> +#undef CONFIG_CMD_NFS
> +
> +/*
> + * Environment
> + */
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +#define CONFIG_ENV_OFFSET (CONFIG_MBR_SIZE \
> + +CONFIG_SBL_SIZE \
need space after +.
> + +CONFIG_BL1_SIZE \
> + +CONFIG_BL2_SIZE)
> +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
> +#define CONFIG_ENV_OVERWRITE
> +/* Default */
> +#define CONFIG_BOOTCOMMAND "fatload mmc 0 40008000 uImage; bootm 40008000"
> +
> +/*
> + * Misc
> + */
> +/* Initialize */
> +#define CONFIG_ARCH_CPU_INIT 1
> +#define CONFIG_BOARD_EARLY_INIT_F 1
> +/* display information */
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +/* Delay */
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_ZERO_BOOTDELAY_CHECK
> +/* TAGS */
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_INITRD_TAG
> +/* Enable devicetree support */
> +#define CONFIG_OF_LIBFDT
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#endif /* __CONFIG_ORIGEN_QUAD_H */
> diff --git a/tools/Makefile b/tools/Makefile
> index 686840a..3da314c 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -68,6 +68,7 @@ BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
> BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
> BIN_FILES-y += mkenvimage$(SFX)
> BIN_FILES-y += mkimage$(SFX)
> +BIN_FILES-$(CONFIG_EXYNOS4) += mk$(BOARD)spl$(SFX)
CONFIG_EXYNOS4? Why?
> BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
> BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
> BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
> @@ -97,6 +98,7 @@ NOPED_OBJ_FILES-y += imximage.o
> NOPED_OBJ_FILES-y += omapimage.o
> NOPED_OBJ_FILES-y += mkenvimage.o
> NOPED_OBJ_FILES-y += mkimage.o
> +OBJ_FILES-$(CONFIG_EXYNOS4) += mkexynosspl.o
> OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
> OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
> OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
>
Thanks.
Minkyu Kang.
More information about the U-Boot
mailing list