[U-Boot] [PATCH 4/4] powerpc/85xx:Update NAND code base to support debugger

[Prabhakar Kushwaha]

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 Applies on http://git.denx.de/u-boot.git branch master

 arch/powerpc/cpu/mpc85xx/start.S |   18 +++++++++++++-----
 1 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 26c32df..2d7b000 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1415,17 +1415,25 @@ relocate_code:
 7:	sync			/* Wait for all icbi to complete on bus */
 	isync
 
-	/*
-	 * Re-point the IVPR at RAM
-	 */
-	mtspr	IVPR,r10
-
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 
 	addi	r0,r10,in_ram - _start + _START_OFFSET
+
+#if defined(CONFIG_E500_V1_V2) && defined(CONFIG_NAND_SPL)
+/*
+ * As IVPR is going to point RAM address,
+ * Make sure IVOR15 has valid opcode to support debugger
+ */
+	mtspr	IVOR15,r0
+#endif
+	/*
+	 * Re-point the IVPR at RAM
+	 */
+	mtspr	IVPR,r10
+
 	mtlr	r0
 	blr				/* NEVER RETURNS! */
 	.globl	in_ram
-- 
1.7.5.4