[U-Boot] [PATCH] MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC

[Kumar Gala]

On Dec 16, 2011, at 4:31 PM, Paul Gortmaker wrote:

> These boards were meaning to deploy this value:
> 
>  #define LCRR_DBYP        0x80000000
> 
> but were missing a zero, and hence toggling a bit that
> lands in an area marked as reserved in the 8548 reference
> manual.
> 
> According to the documentation, LCRR_DBYP should be used as:
> 
>   PLL bypass. This bit should be set when using low bus
>   clock frequencies if the PLL is unable to lock.  When in
>   PLL bypass mode, incoming data is captured in the middle
>   of the bus clock cycle.  It is recommended that PLL bypass
>   mode be used at frequencies of 83 MHz or less.
> 
> So the impact would most likely be undefined behaviour for
> LBC peripherals on boards that were running below 83MHz LBC.
> Looking at the actual u-boot code, the missing DBYP bit was
> meant to be deployed as follows:
> 
>      Between 66 and 133, the DLL is enabled with an
>      override workaround.
> 
> In the future, we'll convert all boards to use the symbolic
> DBYP constant to avoid these "count the zeros" problems, but
> for now, just fix the impacted boards.
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>

applied to 85xx

- k