[U-Boot] mx28 spl power cpu clock configuration

[Fabio Estevam]

Hi Robert,

On 1/25/12, Marek Vasut <marek.vasut at gmail.com> wrote:

>> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock
>> gating - before disabling PLL bypass?
>
> This seems reasonable. Fabio, can you comment?

Could you please post a patch with your proposed change so that we can test it?

Regards,

Fabio Estevam