[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Tom Rini]

On Fri, Jan 20, 2012 at 6:06 AM, Aneesh V <aneesh at ti.com> wrote:
> Hi Christian,
>
>
> On Friday 20 January 2012 06:18 PM, Christian Riesch wrote:
>>
>> Hi Aneesh,
>>
>> On Fri, Jan 20, 2012 at 1:13 PM, Aneesh V<aneesh at ti.com>  wrote:
>>>
>>> On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
>>>>
>>>> On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V<aneesh at ti.com>    wrote:
>>>>>
>>>>> Sughosh,
>>>>
>>>>
>>>> [...]
>>>>>
>>>>>
>>>>> Can you send the value of SCR you found at SPL entry? This will clarify
>>>>> what's enabled and what's not.
>>>>
>>>>
>>>> I would like to try that on my board as well for comparison. Could you
>>>> please tell me how this register can be read? In the ARM manuals SCR
>>>> seems to have several meanings... Thank you!
>>>> Regards, Christian
>>>
>>>
>>> If you have a JTAG based debugger that has the capability of displaying
>>> CP15 registers, look for "CP15 System Control Register". Otherwise you
>>> will have to read it using an assembly instruction like below:
>>>
>>>
>>>        mrc     p15, 0, r0, c1, c0, 0
>>>
>>> After this instruction r0 will contain the SCR value. arm926ejs/start.S
>>> has this instruction at line #367. You can put a breakpoint after this
>>> and look at r0.
>>
>>
>> Thank you!
>>
>> I don't have a JTAG debugger so I stored it in a register, pushed it
>> later to the stack and then read it with md.l from the memory. I tried
>> it on my custom board (AM1808 SoC, direct boot from NOR flash) and on
>> both the da850evm (with AM1808 SoC, AIS boot from SPI flash). The
>> result was the same for both cases, 0x00052078. So DCache and ICache
>> are disabled after the RBL.
>> Regards, Christian
>
>
> Hmm.. That's different from the OMAP processors I have seen. At least
> OMAP4, that I verified again now, leaves the I-cache enabled
> (0x00C51878)
>
> So, Sughosh's problem still remains a mystery:)

So, what do we want to do here?  We really want to get this fix in so
we can get the hawkboard SPL changes in, and the other platforms /
fixups that are gated by that.

If I can sum it up, in the relevant section of code we have incorrect
comments and the init code is not following what the manual says the
correct sequence is.  However, given the (potentially wide) impact the
changes would have, Albert had previously requested making the change
opt-in (but I believe this request came before the "the manual says we
must do ...").  If this is still the case?  If so, can we get an
updated patch?  Thanks!

-- 
Tom