[U-Boot] [PATCH v4 0/6] USB and cache related fixes

[Tom Rini]

Hey all,

In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack.  This change showed a few different problems on TI platforms
(where our cacheline size is 64 not 32).  First, the dcache_off call
that ehci-omap had been doing was now not happening soon enough to paper
over the cache issues.  This call is removed in patch 1.  The second
patch deal with the same problem in EHCI and MUSB.  The USB spec says
that 32 bytes is the minimum alignment but we need larger alignment when
the cache is larger.  Note that we can't use MAX() here as gcc doesn't
allow that expansion inside of align(..).  Patches 3 to 6 disable dcache
support at build time on all platforms that enable CONFIG_USB_EHCI_OMAP
because performing a run-time 'dcache off' operation leaves USB unusable
due to the unaligned flushes that are still attempted.  Run-time testing
on an omap3_beagle shows a very slight (less than half a second, checked
with grabserial) increase in load time for a 3.5-rc3 kernel image from
SD card.  Note that otherwise a tftp load takes minutes to complete
rather than seconds due to all of the console spam.

Tested on omap3_beagle (which was previously broken) and a MAKEALL -a arm
looks good too.

Changes in v4:
- Drop alignment on rootdev/hccr/hcor as a double-check showed that was
  masking an alignment problem elsewhere (Marek Vasut)

Changes in v3:
- Drop the cache_v7.c change and instead make all CONFIG_USB_EHCI_OMAP boards
  disable DCACHE at build time.

Changes in v2:
- Condense last two patches into one that puts the test into <usb.h>

-- 
Tom