[U-Boot] [PATCH 8/9] tegra2: Remove CPU init code from tegra2 u-boot
Allen Martin
amartin at nvidia.com
Thu May 10 09:02:26 CEST 2012
This code is now included in the tegra2 SPL
Signed-off-by: Allen Martin <amartin at nvidia.com>
---
arch/arm/cpu/armv7/start.S | 2 -
arch/arm/cpu/tegra2-common/ap20.c | 257 +-----------------------------------
arch/arm/cpu/tegra2-common/ap20.h | 102 --------------
arch/arm/cpu/tegra2-common/board.c | 22 ---
include/configs/tegra2-common.h | 4 -
5 files changed, 3 insertions(+), 384 deletions(-)
delete mode 100644 arch/arm/cpu/tegra2-common/ap20.h
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index ef08a55..6a77c71 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -132,7 +132,6 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA2)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -148,7 +147,6 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra2 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/cpu/tegra2-common/ap20.c b/arch/arm/cpu/tegra2-common/ap20.c
index b749821..cb8fcdf 100644
--- a/arch/arm/cpu/tegra2-common/ap20.c
+++ b/arch/arm/cpu/tegra2-common/ap20.c
@@ -20,244 +20,12 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
-#include "ap20.h"
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
-#include <asm/arch/clk_rst.h>
-#include <asm/arch/clock.h>
#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
#include <asm/arch/scu.h>
#include <common.h>
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-static int ap20_cpu_is_cortexa9(void)
-{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
- return;
-
- /* Set PLLX_MISC */
- writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
-
- /* Use 12MHz clock here */
- reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
- reg |= 1000 << PLL_DIVN_SHIFT;
- writel(reg, &pll->pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
-
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
- * NOTE:
- * Regardless of whether the request is to enable or disable the CPU
- * clock, every processor in the CPU complex except the master (CPU 0)
- * will have it's clock stopped because the AVP only talks to the
- * master. The AVP does not know (nor does it need to know) that there
- * are multiple processors in the CPU complex.
- */
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
- * Read the register containing the individual CPU clock enables and
- * always stop the clock to CPU 1.
- */
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
- u32 reg;
-
- /* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-static void powerup_cpu(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
- u32 reg;
- int timeout = IO_STABILIZATION_DELAY;
-
- if (!is_cpu_powered()) {
- /* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
- reg &= PARTID_CP;
- reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_cpu_powered()) {
- if (timeout-- == 0)
- printf("CPU failed to power up!\n");
- else
- udelay(10);
- }
-
- /*
- * Remove the I/O clamps from CPU power partition.
- * Recommended only on a Warm boot, if the CPU partition gets
- * power gated. Shouldn't cause any harm when called after a
- * cold boot according to HW, probably just redundant.
- */
- remove_cpu_io_clamps();
- }
-}
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
- u32 reg;
-
- reg = readl(&pmc->pmc_cntrl);
- reg |= CPUPWRREQ_OE;
- writel(reg, &pmc->pmc_cntrl);
-
- /*
- * The TI PMU65861C needs a 3.75ms delay between enabling
- * the power rail and enabling the CPU clock. This delay
- * between SM1EN and SM1 is for switching time + the ramp
- * up of the voltage to the CPU (VDD_CPU from PMU).
- */
- udelay(3750);
-}
-
-static void reset_A9_cpu(int reset)
-{
- /*
- * NOTE: Regardless of whether the request is to hold the CPU in reset
- * or take it out of reset, every processor in the CPU complex
- * except the master (CPU 0) will be held in reset because the
- * AVP only talks to the master. The AVP does not know that there
- * are multiple processors in the CPU complex.
- */
-
- /* Hold CPU 1 in reset, and CPU 0 if asked */
- reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
- reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
- reset);
-
- /* Enable/Disable master CPU reset */
- reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-static void clock_enable_coresight(int enable)
-{
- u32 rst, src;
-
- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
- if (enable) {
- /*
- * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
- * 1.5, giving an effective frequency of 144MHz.
- * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
- * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
- */
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
- /* Unlock the CPU CoreSight interfaces */
- rst = 0xC5ACCE55;
- writel(rst, CSITE_CPU_DBG0_LAR);
- writel(rst, CSITE_CPU_DBG1_LAR);
- }
-}
-
-void start_cpu(u32 reset_vector)
-{
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- /* Hold the CPUs in reset */
- reset_A9_cpu(1);
-
- /* Disable the CPU clock */
- enable_cpu_clock(0);
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
- */
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Enable the CPU clock */
- enable_cpu_clock(1);
-
- /* If the CPU doesn't already have power, power it up */
- powerup_cpu();
-
- /* Take the CPU out of reset */
- reset_A9_cpu(0);
-}
-
-
-void halt_avp(void)
-{
- for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
- }
-}
-
-void enable_scu(void)
+static void enable_scu(void)
{
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
u32 reg;
@@ -275,7 +43,7 @@ void enable_scu(void)
writel(reg, &scu->scu_ctrl);
}
-void init_pmc_scratch(void)
+static void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
int i;
@@ -288,27 +56,8 @@ void init_pmc_scratch(void)
writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
}
-void tegra2_start(void)
+void lowlevel_init(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
- /* If we are the AVP, start up the first Cortex-A9 */
- if (!ap20_cpu_is_cortexa9()) {
- /* enable JTAG */
- writel(0xC0, &pmt->pmt_cfg_ctl);
-
- /*
- * If we are ARM7 - give it a different stack. We are about to
- * start up the A9 which will want to use this one.
- */
- asm volatile("mov sp, %0\n"
- : : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
-
- start_cpu((u32)_start);
- halt_avp();
- /* not reached */
- }
-
/* Init PMC scratch memory */
init_pmc_scratch();
diff --git a/arch/arm/cpu/tegra2-common/ap20.h b/arch/arm/cpu/tegra2-common/ap20.h
deleted file mode 100644
index a4b4d73..0000000
--- a/arch/arm/cpu/tegra2-common/ap20.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
-#define IO_STABILIZATION_DELAY (1000)
-
-#define NVBL_PLLP_KHZ (216000)
-
-#define PLLX_ENABLED (1 << 30)
-#define CCLK_BURST_POLICY 0x20008888
-#define SUPER_CCLK_DIVIDER 0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0 0x0
-
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM 0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM 0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE 0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH 0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- * stack is placed below the AVP stack. Once the CPU stack has been moved,
- * the AVP is free to use the IRAM the CPU stack previously occupied if
- * it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- * CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT \
- (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT \
- (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP 2
-#define HALT_COP_EVENT_JTAG (1 << 28)
-#define HALT_COP_EVENT_IRQ_1 (1 << 11)
-#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-
-/* Start up the tegra2 SOC */
-void tegra2_start(void);
-
-/* This is the main entry into U-Boot, used by the Cortex-A9 */
-extern void _start(void);
diff --git a/arch/arm/cpu/tegra2-common/board.c b/arch/arm/cpu/tegra2-common/board.c
index a797e6f..9874bb2 100644
--- a/arch/arm/cpu/tegra2-common/board.c
+++ b/arch/arm/cpu/tegra2-common/board.c
@@ -23,7 +23,6 @@
#include <common.h>
#include <asm/io.h>
-#include "ap20.h"
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/sys_proto.h>
@@ -80,27 +79,6 @@ int checkboard(void)
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * Note this function is executed by the ARM7TDMI AVP. It does not return
- * in this case. It is also called once the A9 starts up, but does nothing in
- * that case.
- */
-int arch_cpu_init(void)
-{
- /* Fire up the Cortex A9 */
- tegra2_start();
-
- /* We didn't do this init in start.S, so do it now */
- cpu_init_cp15();
-
- /* Initialize essential common plls */
- clock_early_init();
-
- return 0;
-}
-#endif
-
/**
* Set up the specified uarts
*
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 997887a..4828bfd 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -35,8 +35,6 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
-
#include <asm/arch/tegra2.h> /* get chip and board defs */
/*
@@ -45,8 +43,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
--
1.7.9.5
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