[U-Boot] [PATCH 9/9] mx6qsabrelite: Add splaschscreen support
Fabio Estevam
fabio.estevam at freescale.com
Thu May 31 19:24:03 CEST 2012
Add splaschscreen support.
It was used a Hannstar 1024 x 768 LVDS panel that can be connected to the mx6qsabrelite board.
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
I understand this patch will need to be improved, but I am posting it now, so that others
can possibly test it.
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 112 +++++++++++++++++++++++++
include/configs/mx6qsabrelite.h | 21 +++++-
2 files changed, 132 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 29cbfed..6aff947 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -33,6 +33,9 @@
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
@@ -55,6 +58,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -143,6 +151,25 @@ static iomux_v3_cfg_t button_pads[] = {
MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
};
+iomux_v3_cfg_t lcd_gpio[] = {
+ MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t i2c3_pads[] = {
+ MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
+static void setup_iomux_i2c3(void)
+{
+#define CLKCTL_CCGR2 0x70
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+ /* Enable i2c clock */
+ int reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+ reg |= 0xC00;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+}
+
static void setup_iomux_enet(void)
{
gpio_direction_output(87, 0); /* GPIO 3-23 */
@@ -320,10 +347,85 @@ int setup_sata(void)
}
#endif
+static struct fb_videomode lvds_xga = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+void lcd_iomux(void)
+{
+ int reg;
+ /* Turn on GPIO backlight */
+ imx_iomux_v3_setup_multiple_pads(lcd_gpio, ARRAY_SIZE(lcd_gpio));
+ gpio_direction_output(18, 1);
+
+#define CLKCTL_CGR3 0x38
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CCGR3 0x74
+ /* Turn on IPU clock */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
+ reg |= 0x300F;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
+
+ reg = readl(ANATOP_BASE_ADDR + 0xF0);
+ reg &= ~0x00003F00;
+ reg |= 0x00001300;
+ writel(reg, ANATOP_BASE_ADDR + 0xF4);
+
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+ reg &= ~0x00007E00;
+ reg |= 0x00003600;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
+ reg |= 0x00000C00;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
+
+ reg = 0x0002A953;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
+
+ writel(0x201, IOMUXC_BASE_ADDR + 0x8);
+}
+
+void lcd_enable(void)
+{
+
+ int ret = ipuv3_fb_init(&lvds_xga, 0, IPU_PIX_FMT_RGB666);
+ if (ret)
+ printf("LCD cannot be configured: %d\n", ret);
+}
+
+void setup_lvds_poweron(void)
+{
+ uchar value;
+
+ i2c_read(0x1f, 3, 1, &value, 1);
+ value &= ~0x2;
+ i2c_write(0x1f, 3, 1, &value, 1);
+ i2c_read(0x1f, 1, 1, &value, 1);
+ value |= 0x2;
+ i2c_write(0x1f, 1, 1, &value, 1);
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
setup_buttons();
+ lcd_iomux();
+ setup_iomux_i2c3();
return 0;
}
@@ -341,9 +443,19 @@ int board_init(void)
setup_sata();
#endif
+#ifdef CONFIG_VIDEO
+ lcd_enable();
+#endif
return 0;
}
+int board_late_init(void)
+{
+ setup_lvds_poweron();
+ setenv("stdout", "serial");
+ return 0;
+}
+
int checkboard(void)
{
puts("Board: MX6Q-Sabre Lite\n");
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index feabc05..79b7db7 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -38,10 +38,11 @@
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
@@ -111,6 +112,24 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+
+/* I2C Configs */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX6Q_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x1f
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.1
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