[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP

[Marek Vasut]

Dear Joe Hershberger,

> Hi Marek,
> 
> On Thu, Sep 13, 2012 at 4:28 AM, Marek Vasut <marex at denx.de> wrote:
> > Dear Michal Simek,
> > 
> >> +     /*
> >> +      * Following is the setup for Network Control register.
> >> +      * Bit 2:  Set to enable Receive operation.
> >> +      * Bit 3:  Set to enable Transmitt operation.
> >> +      * Bit 4:  Set to enable MDIO operation.
> >> +      */
> >> +     tmp = readl(&regs->nwctrl);
> >> +     /* MDIO, Rx and Tx enable */
> >> +     tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
> >> +         ZYNQ_GEM_NWCTRL_TXEN_MASK;
> >> +     writel(tmp, &regs->nwctrl);
> > 
> > setbits_le32()
> 
> This is not equivalent.  Using setbits_le32() will not provide a dmb()
> on the operations the way that readl(), writel() does.  I believe this
> will cause problems when the dcache is enabled, right?

Not when dcache is enabled, the register space isn't cached. But the compiler 
can run some wild optimizations across that. So where's the problem, do we add 
dmb() to clrsetbits() calls ?

> -Joe

Best regards,
Marek Vasut