[U-Boot] [PATCH] mtd: nand: omap: fix ecc-layout for HAM1 ecc-scheme

[Stefan Roese]

On 05.12.2013 13:24, Pekon Gupta wrote:
> As per OMAP3530 TRM referenced below [1]
> 
> For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
>  - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
>  - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device
> 
> Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
>  *for x8 NAND Device*
>  +--------+---------+---------+---------+---------+---------+---------+
>  | xxxx   | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
>  +--------+---------+---------+---------+---------+---------+---------+
> 
>  *for x16 NAND Device*
>  +--------+--------+---------+---------+---------+---------+---------+---------+
>  | xxxxx  | xxxxx  | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
>  +--------+--------+---------+---------+---------+---------+---------+---------+
> 
> This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
> For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.
> 
> [1] OMAP3530: http://www.ti.com/product/omap3530
>     TRM: http://www.ti.com/litv/pdf/spruf98x
> 		Chapter-25: Initialization Sub-topic: Memory Booting
> 		Section: 25.4.7.4 NAND
> 		Figure 25-19. ECC Locations in NAND Spare Areas
> 
> Reported-by: Stefan Roese <sr at denx.de>
> Signed-off-by: Pekon Gupta <pekon at ti.com>

This fixes the problem I reported. Tested again on x8 and x16 NAND
OMAP3530 targets. Thanks Pekon!

Tested-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan