[U-Boot] [PATCH 3/3] PPC 85xx: Add qemu-ppce500 machine
Alexander Graf
agraf at suse.de
Sun Jan 19 16:19:02 CET 2014
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.
It also provides more PCI slots and is supposed to be enumerated by
device tree only.
This patch adds support for the current generation ppce500 machine as
it is implemented today.
Signed-off-by: Alexander Graf <agraf at suse.de>
---
arch/powerpc/cpu/mpc85xx/start.S | 7 +
arch/powerpc/include/asm/config_mpc85xx.h | 4 +
board/freescale/qemu-ppce500/Makefile | 10 ++
board/freescale/qemu-ppce500/qemu-ppce500.c | 260 +++++++++++++++++++++++++++
board/freescale/qemu-ppce500/tlb.c | 59 ++++++
boards.cfg | 1 +
include/configs/qemu-ppce500.h | 235 ++++++++++++++++++++++++
7 files changed, 576 insertions(+)
create mode 100644 board/freescale/qemu-ppce500/Makefile
create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c
create mode 100644 board/freescale/qemu-ppce500/tlb.c
create mode 100644 include/configs/qemu-ppce500.h
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10..ccbcc03 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,6 +80,13 @@ _start_e500:
li r1,MSR_DE
mtmsr r1
+#ifdef CONFIG_QEMU_E500
+ /* Save our ePAPR device tree off before we clobber it */
+ lis r2, CONFIG_QEMU_DT_ADDR at h
+ ori r2, r2, CONFIG_QEMU_DT_ADDR at l
+ stw r3, 0(r2)
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f0..a0ab453 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -776,6 +776,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#elif defined(CONFIG_QEMU_E500)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
+
#else
#error Processor type not defined for this platform
#endif
diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile
new file mode 100644
index 0000000..193b160
--- /dev/null
+++ b/board/freescale/qemu-ppce500/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += qemu-ppce500.o
+obj-y += tlb.o
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
new file mode 100644
index 0000000..c6c4b4a
--- /dev/null
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <malloc.h>
+
+int checkboard(void)
+{
+ return 0;
+}
+
+static struct pci_controller pci1_hose;
+
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info;
+ u32 devdisr, pordevsr;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+
+ puts("\n");
+
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info.regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI: disabled\n");
+ }
+
+ puts("\n");
+}
+
+int last_stage_init(void)
+{
+ int ret;
+ int len = 0;
+ const void *prop;
+ int chosen;
+ uint32_t *dt_base_ptr = (void*)CONFIG_QEMU_DT_ADDR;
+ uint32_t dt_base = *dt_base_ptr;
+ uint32_t dt_size;
+ void *fdt;
+
+ dt_size = fdt_totalsize((void*)dt_base);
+
+ /* Reserve 4k for dtb tweaks */
+ dt_size += 4096;
+ fdt = malloc(dt_size);
+
+ /* Open device tree */
+ ret = fdt_open_into((void*)dt_base, fdt, dt_size);
+ if (ret) {
+ printf("Couldn't open fdt at %x\n", dt_base);
+ return -EIO;
+ }
+
+ chosen = fdt_path_offset(fdt, "/chosen");
+ if (chosen < 0) {
+ printf("Couldn't find /chosen node in fdt\n");
+ return -EIO;
+ }
+
+ prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
+ if (prop && (len >= 8)) {
+ /* -kernel boot */
+ setenv_hex("kernel_addr", *(uint64_t*)prop);
+
+ /*
+ * We already know where the initrd is inside the dtb, so no
+ * need to override it
+ */
+ setenv("ramdisk_addr", "-");
+ }
+
+ /* Give the user a variable for the host fdt */
+ setenv_hex("fdt_addr", (int)dt_base);
+
+ free(fdt);
+
+ return 0;
+}
+
+static uint64_t get_linear_ram_size(void)
+{
+ const void *prop;
+ int memory;
+ int len;
+ uint32_t *dt_base_ptr = (void*)CONFIG_QEMU_DT_ADDR;
+ void *fdt = &dt_base_ptr[1];
+ int ret;
+ uint32_t dt_base = *dt_base_ptr;
+ uint32_t dt_size = 1024 * 1024;
+
+ ret = fdt_open_into((void*)dt_base, fdt, dt_size);
+ if (ret)
+ panic("Couldn't open fdt");
+
+ memory = fdt_path_offset(fdt, "/memory");
+ prop = fdt_getprop(fdt, memory, "reg", &len);
+
+ if (prop && len >= 16)
+ return *(uint64_t*)(prop+8);
+
+ panic("Couldn't determine RAM size");
+}
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ /* The actual clock doesn't matter in a PV machine */
+ return 33333333;
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+ return 0;
+}
+
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif
+
+void print_laws(void)
+{
+ /* We don't emulate LAWs yet */
+}
+
+static void fixup_tlb1(uint64_t ram_size)
+{
+ u32 mas0, mas1, mas2, mas3, mas7;
+ long tmp;
+
+ /* Flush TLB0 - it only contains stale maps by now */
+ invalidate_tlb(0);
+
+ /* Create a temporary AS=1 map for ourselves */
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_64M);
+ mas2 = FSL_BOOKE_MAS2(0, 0);
+ mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_DDR_SDRAM_BASE, 0,
+ MAS3_SW|MAS3_SR|MAS3_SX);
+ mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_DDR_SDRAM_BASE);
+
+ write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+ /* Enter AS=1 */
+ asm volatile(
+ "mfmsr %0 \n"
+ "ori %0, %0, 0x30 \n"
+ "mtsrr1 %0 \n"
+ "bl 1f \n"
+ "1: \n"
+ "mflr %0 \n"
+ "addi %0, %0, 16 \n"
+ "mtsrr0 %0 \n"
+ "rfi \n"
+ : "=r"(tmp) : : "lr");
+
+ /* Now we live in AS=1, so we can flush all old maps */
+ clear_ddr_tlbs(ram_size >> 20);
+ /* and create new ones */
+ setup_ddr_tlbs(ram_size >> 20);
+
+ /* Now we can safely go back to AS=0 */
+ asm volatile(
+ "mfmsr %0 \n"
+ "subi %0, %0, 0x30 \n"
+ "mtsrr1 %0 \n"
+ "bl 1f \n"
+ "1: \n"
+ "mflr %0 \n"
+ "addi %0, %0, 16 \n"
+ "mtsrr0 %0 \n"
+ "rfi \n"
+ : "=r"(tmp) : : "lr");
+
+ /* And remove our AS=1 map */
+ disable_tlb(13);
+}
+
+phys_size_t fixed_sdram(void)
+{
+ uint64_t ram_size;
+
+ ram_size = get_linear_ram_size();
+
+ /*
+ * At this point we know that we're running in RAM, but within the
+ * first 64MB because we don't have a mapping for anything else.
+ *
+ * Replace that mapping with real maps for our full RAM range.
+ */
+ fixup_tlb1(ram_size);
+
+ return ram_size;
+}
+
+phys_size_t fsl_ddr_sdram_size(void)
+{
+ return fixed_sdram();
+}
+
+void init_laws(void)
+{
+ /* We don't emulate LAWs yet */
+}
+
+int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
+{
+ /* We don't emulate LAWs yet */
+ return 0;
+}
diff --git a/board/freescale/qemu-ppce500/tlb.c b/board/freescale/qemu-ppce500/tlb.c
new file mode 100644
index 0000000..cdc7013
--- /dev/null
+++ b/board/freescale/qemu-ppce500/tlb.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ /*
+ * TLB 0: 64M Cacheable
+ * 0x00000000 64M Covers RAM at 0x00000000
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe100_0000 255M PCI IO range
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_64M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index d177f82..ab50982 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -986,6 +986,7 @@ Active powerpc mpc85xx - freescale t2080qds
Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf at suse.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach at gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach at gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach at gdsys.de>
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
new file mode 100644
index 0000000..981b016
--- /dev/null
+++ b/include/configs/qemu-ppce500.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __QEMU_PPCE500_H
+#define __QEMU_PPCE500_H
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_QEMU_E500
+
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xf00000 /* 15 MB */
+
+#undef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS (0x1000000 - 4) /* 16 MB */
+
+#define CONFIG_SYS_RAMBOOT
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR 0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+#define CONFIG_FW_CFG_ADDR 0xFF7FFFFC
+#define CONFIG_QEMU_DT_ADDR ((2 * 1024 * 1024) - 4) /* below 2MB */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 0
+#define CONFIG_CHIP_SELECTS_PER_CTRL 0
+
+/* Get RAM size from device tree */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+
+
+/*
+ * IFC Definitions
+ */
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
+#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
+
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_RESET_VECTOR_ADDRESS - 0x100000 + 4)
+#define CONFIG_SYS_SDRAM_SIZE 64
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
+#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#define CONFIG_LBA48
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND \
+ "test -n \"$kernel_addr\" && bootm $kernel_addr $ramdisk_addr $fdt_addr\0"
+
+#endif /* __QEMU_PPCE500_H */
--
1.7.10.4
More information about the U-Boot
mailing list