[U-Boot] socfpga: time problems, get ethernet to work in recent versions
Pavel Machek
pavel at denx.de
Fri Jul 11 08:43:26 CEST 2014
Hi!
> After extensive debugging, I found out that recent u-boot gets time
> very wrong (at least 1000 times too fast), and that was breaking all
> my attempts at getting networking to work.
...
> I also reverted to old version of driver for debugging and probably
> broke a lot of stuff.
>
> Anyway, below is patch you don't want to read, but that does the trick
> for me. Now that ethernet started to work, I'm sure I'll be able to
> strip it down to something reasonable.
Below is new version. Still not clean, but 1000 lines instead of 2200.
> In the meantime, hints how to solve the "time goes way too fast" in
> clean way would be welcome. I increased
>
> #define CONFIG_SYS_TIMER_RATE 25000000
>
> by factor of 1000, then by factor of 1000000, and time was still too
> fast. Hmm, maybe LL is needed there?
Its getting strange.
Very big CONFIG_SYS_TIMER_RATEs do not work, as it is stored in ulong.
But why is time too fast by factor of 20 000 000? Or maybe it is
25 000 000...?
Best regards,
Pavel
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f564046..c8e925a 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -14,5 +14,8 @@
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
+
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index a960eb6..4f6d760 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -7,11 +7,39 @@
#include <common.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
+#ifndef CONFIG_SPL_BUILD
+#include <phy.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include "../../../drivers/net/designware.h"
+#endif
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+#define RSTMGR_PERMODRST_EMAC0_LSB 0
+#define RSTMGR_PERMODRST_EMAC1_LSB 1
+
+#define CONFIG_SYSMGR_EMAC_CTRL (SOCFPGA_SYSMGR_ADDRESS + 0x60)
+
+/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+
+/* EMAC controller and PHY used */
+#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
+#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
+#define CONFIG_PHY_INTERFACE_MODE SOCFPGA_PHYSEL_ENUM_RGMII
+
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
@@ -28,7 +56,7 @@ int print_cpuinfo(void)
*/
int checkboard(void)
{
- puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+ puts("BOARD : " ALTERA_BOARD_NAME "\n");
return 0;
}
@@ -64,8 +92,159 @@ int overwrite_console(void)
/*
* DesignWare Ethernet initialization
*/
+
+int designware_board_phy_init(struct eth_device *dev, int phy_addr,
+ int (*mii_write)(struct eth_device *, u8, u8, u16),
+ int (*dw_reset_phy)(struct eth_device *))
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+
+ printf("Back to board file\n");
+
+#if 0
+ if ((*dw_reset_phy)(dev) < 0)
+ return -1;
+#endif
+
+ return 0;
+
+ bus = mdio_get_current_dev();
+ printf("Board file: bus %lx\n", bus);
+
+ phy_addr = phy_find_by_mask(bus, 0xffffffff, PHY_INTERFACE_MODE_RGMII);
+ printf("Board file: phy addr %lx\n", phy_addr);
+
+ /*
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
+phy_interface_t interface)
+ */
+
+ phydev = phy_connect(bus, phy_addr, dev,
+ priv->interface);
+
+ printf("Board file: bus %lx\n", phydev);
+ /* Micrel PHY is connected to EMAC1 */
+ if (strcasecmp(phydev->drv->name, "Micrel ksz9021") == 0 &&
+ ((phydev->drv->uid & phydev->drv->mask) ==
+ (phydev->phy_id & phydev->drv->mask))) {
+
+ printf("Configuring PHY skew timing for %s\n",
+ phydev->drv->name);
+
+ /* min rx data delay */
+ if (ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16,
+ CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0)
+ return -1;
+ /* min tx data delay */
+ if (ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16,
+ CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0)
+ return -1;
+ /* max rx/tx clock delay, min rx/tx control */
+ if (ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ getenv_ulong(CONFIG_KSZ9021_CLK_SKEW_ENV, 16,
+ CONFIG_KSZ9021_CLK_SKEW_VAL)) < 0)
+ return -1;
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ }
+ return 0;
+}
+
+/* Change the reset state for EMAC0 */
+void emac0_reset_enable(uint state)
+{
+ if (state)
+ setbits_le32(&reset_manager_base->per_mod_reset,
+ (1 << RSTMGR_PERMODRST_EMAC0_LSB));
+ else
+ clrbits_le32(&reset_manager_base->per_mod_reset,
+ (1 << RSTMGR_PERMODRST_EMAC0_LSB));
+}
+
+/* Change the reset state for EMAC1 */
+void emac1_reset_enable(uint state)
+{
+ if (state)
+ setbits_le32(&reset_manager_base->per_mod_reset,
+ (1 << RSTMGR_PERMODRST_EMAC1_LSB));
+ else
+ clrbits_le32(&reset_manager_base->per_mod_reset,
+ (1 << RSTMGR_PERMODRST_EMAC1_LSB));
+}
+
+
/* We know all the init functions have been run now */
int board_eth_init(bd_t *bis)
{
- return 0;
+ printf("Board_eth_init\n");
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && \
+!defined(CONFIG_SPL_BUILD)
+
+ /* Initialize EMAC */
+
+ /*
+ * Putting the EMAC controller to reset when configuring the PHY
+ * interface select at System Manager
+ */
+ printf("enabling resets...\n");
+ emac0_reset_enable(1);
+ emac1_reset_enable(1);
+
+ /* Clearing emac0 PHY interface select to 0 */
+ clrbits_le32(CONFIG_SYSMGR_EMAC_CTRL,
+ (SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+#if (CONFIG_EMAC_BASE == CONFIG_EMAC0_BASE)
+ SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB));
+#elif (CONFIG_EMAC_BASE == CONFIG_EMAC1_BASE)
+ SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB));
+#endif
+
+ /* configure to PHY interface select choosed */
+ setbits_le32(CONFIG_SYSMGR_EMAC_CTRL,
+#if (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_GMII)
+ (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII <<
+#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_MII)
+ (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII <<
+#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RGMII)
+ (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII <<
+#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RMII)
+ (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII <<
+#endif
+#if (CONFIG_EMAC_BASE == CONFIG_EMAC0_BASE)
+ SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB));
+ printf("enabling emac0...\n");
+ /* Release the EMAC controller from reset */
+ emac0_reset_enable(0);
+#elif (CONFIG_EMAC_BASE == CONFIG_EMAC1_BASE)
+ SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB));
+ printf("enabling emac1...\n");
+ /* Release the EMAC controller from reset */
+ emac1_reset_enable(0);
+#endif
+
+ /* initialize and register the emac */
+ int rval = designware_initialize(CONFIG_EMAC_BASE, /*
+ CONFIG_EPHY_PHY_ADDR, */
+#if (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_GMII)
+ PHY_INTERFACE_MODE_GMII);
+#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_MII)
+ PHY_INTERFACE_MODE_MII);
+#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RGMII)
+ PHY_INTERFACE_MODE_RGMII);
+#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RMII)
+ PHY_INTERFACE_MODE_RMII);
+#endif
+ printf("board_eth_init %d\n", rval);
+ return rval;
+#else
+ return 0;
+#endif
}
diff --git a/boards.cfg b/boards.cfg
index 221b7f8..6eebbf5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -379,6 +379,8 @@ Active arm armv7 rmobile renesas lager
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak at samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang at samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
+Active arm armv7 socfpga altera socfpga socfpga_virtual - -
+Active arm armv7 socfpga altera socfpga socfpga_socrates - -
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier at linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965 at freescale.com>
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 78751b2..499cdd9 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -376,6 +376,38 @@ static int dw_eth_recv(struct eth_device *dev)
return length;
}
+#if 0 // defined(CONFIG_DW_SEARCH_PHY)
+/* This is somehow all wrong :-( */
+static int find_phy(struct mii_dev *bus)
+{
+ int phy_addr = 0;
+ u16 ctrl, oldctrl;
+
+ do {
+ printf("trying phy addr %d\n", phy_addr);
+ bus->read(bus, phy_addr, MII_BMCR, &ctrl);
+ oldctrl = ctrl & BMCR_ANENABLE;
+
+ ctrl ^= BMCR_ANENABLE;
+ bus->write(bus, phy_addr, MII_BMCR, ctrl);
+ bus->read(bus, phy_addr, MII_BMCR, &ctrl);
+ ctrl &= BMCR_ANENABLE;
+
+ if (ctrl == oldctrl) {
+ phy_addr++;
+ } else {
+ ctrl ^= BMCR_ANENABLE;
+ bus->write(bus, phy_addr, MII_BMCR, ctrl);
+ printf("found phy addr %d\n", phy_addr);
+ return phy_addr;
+ }
+ } while (phy_addr < 32);
+
+ return -1;
+}
+#endif
+
+
static int dw_phy_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
@@ -386,15 +418,21 @@ static int dw_phy_init(struct eth_device *dev)
mask = 1 << CONFIG_PHY_ADDR;
#endif
+ printf("Searching for phy\n");
+ //find_phy(dev);
+
+ printf("find_by_mask\n");
phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
if (!phydev)
return -1;
+ printf("connect_dev\n");
phy_connect_dev(phydev, dev);
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
+ printf("phy_config\n");
priv->phydev = phydev;
phy_config(phydev);
@@ -406,6 +444,8 @@ int designware_initialize(ulong base_addr, u32 interface)
struct eth_device *dev;
struct dw_eth_dev *priv;
+
+ printf("designware_initialize\n");
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
if (!dev)
return -ENOMEM;
@@ -432,12 +472,14 @@ int designware_initialize(ulong base_addr, u32 interface)
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
DW_DMA_BASE_OFFSET);
+ printf("eth register\n");
dev->init = dw_eth_init;
dev->send = dw_eth_send;
dev->recv = dw_eth_recv;
dev->halt = dw_eth_halt;
dev->write_hwaddr = dw_write_hwaddr;
+ printk("eth_register\n");
eth_register(dev);
priv->interface = interface;
@@ -445,5 +487,8 @@ int designware_initialize(ulong base_addr, u32 interface)
dw_mdio_init(dev->name, priv->mac_regs_p);
priv->bus = miiphy_get_dev_by_name(dev->name);
+ designware_board_phy_init(dev, 0, NULL, NULL);
+
+ printk("dw_phy_init\n");
return dw_phy_init(dev);
}
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5d7e3be..506efb2 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -53,6 +53,8 @@ static struct phy_driver KS8721_driver = {
static int ksz90xx_startup(struct phy_device *phydev)
{
unsigned phy_ctl;
+
+ printf("ksz90xx_startup\n");
genphy_update_link(phydev);
phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
@@ -215,6 +217,7 @@ static struct phy_driver ksz9031_driver = {
int phy_micrel_init(void)
{
+ printf("phy_micrel_init\n");
phy_register(&KSZ804_driver);
#ifdef CONFIG_PHY_MICREL_KSZ9021
phy_register(&ksz9021_driver);
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
new file mode 100644
index 0000000..ded6cb6
--- /dev/null
+++ b/include/configs/socfpga_common.h
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_COMMON_H
+#define __CONFIG_COMMON_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE 0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE 0x01000040
+#endif
+#define CONFIG_SYS_LOAD_ADDR 0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE 1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY 3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=uImage\0" \
+ "fdt_addr=100\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE 0x40000000
+
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 1000000
+#else
+#define V_NS16550_CLK 100000000
+#endif
+#define CONFIG_BAUDRATE 57600
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+/* Timer info */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE 2400000
+#else
+#define CONFIG_SYS_TIMER_RATE 25000000
+#endif
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * network support
+ */
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_DESIGNWARE_ETH 1
+#endif
+
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
+/* console support for network */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+/* designware */
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+/* phy */
+#define CONFIG_EPHY0_PHY_ADDR 0
+#define CONFIG_EPHY1_PHY_ADDR 4
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+/* Type of PHY available */
+#define SOCFPGA_PHYSEL_ENUM_GMII 0x0
+#define SOCFPGA_PHYSEL_ENUM_MII 0x1
+#define SOCFPGA_PHYSEL_ENUM_RGMII 0x2
+#define SOCFPGA_PHYSEL_ENUM_RMII 0x3
+#endif /* CONFIG_DESIGNWARE_ETH */
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE (4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CHUNKSZ_CRC32 (1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif /* __CONFIG_COMMON_H */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 0254249..d5d59d2 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -1,240 +1,16 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Pavel Machek <pavel at denx.de>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/socfpga_base_addrs.h>
-#include "../../board/altera/socfpga/pinmux_config.h"
-#include "../../board/altera/socfpga/pll_config.h"
-
-/*
- * High level configuration
- */
/* Virtual target or real hardware */
-#define CONFIG_SOCFPGA_VIRTUAL_TARGET
-
-#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_USE_IRQ
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SINGLE_BOOTLOADER
-#define CONFIG_SOCFPGA
-
-/* base address for .text section */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE 0x08000040
-#else
-#define CONFIG_SYS_TEXT_BASE 0x01000040
-#endif
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/*
- * Display CPU and Board Info
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
- * Enable early stage initialization at C environment
- */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* flat device tree */
-#define CONFIG_OF_LIBFDT
-/* skip updating the FDT blob */
-#define CONFIG_FDT_BLOB_SKIP_UPDATE
-/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
-#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
-
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
-
-/*
- * Memory allocation (MALLOC)
- */
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE 1024
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* SP location before relocation, must use scratch RAM */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-/* Reserving 0x100 space at back of scratch RAM for debug info */
-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
-/* Stack pointer prior relocation, must situated at on-chip RAM */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-/* FAT file system support */
-#define CONFIG_CMD_FAT
-
-
-/*
- * Misc
- */
-#define CONFIG_DOS_PARTITION 1
-
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
-#endif
-
-/*
- * Environment setup
- */
-
-/* Delay before automatically booting the default image */
-#define CONFIG_BOOTDELAY 3
-/* Enable auto completion of commands using TAB */
-#define CONFIG_AUTO_COMPLETE
-/* use "hush" command parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_CMD_RUN
-
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-/*
- * arguments passed to the bootm command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will overide also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "bootimage=uImage\0" \
- "fdt_addr=100\0" \
- "fsloadcmd=ext2load\0" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
- "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
-
-/* using environment setting for stdin, stdout, stderr */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* Enable the call to overwrite_console() */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-/* Enable overwrite of previous console environment settings */
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-
-/*
- * Hardware drivers
- */
-
-/*
- * SDRAM Memory Map
- */
-/* We have 1 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-/* SDRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x40000000
-
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
-
-/*
- * NS16550 Configuration
- */
-#define UART0_BASE SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define V_NS16550_CLK 1000000
-#else
-#define V_NS16550_CLK 100000000
-#endif
-#define CONFIG_BAUDRATE 115200
-
-/*
- * FLASH
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * L4 OSC1 Timer 0
- */
-/* This timer use eosc1 where the clock frequency is fixed
- * throughout any condition */
-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL 0xFFFFFFFF
-/* Timer info */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE 2400000
-#else
-#define CONFIG_SYS_TIMER_RATE 25000000
-#endif
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/*
- * SPL "Second Program Loader" aka Initial Software
- */
-
-/* Enable building of SPL globally */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-
-/* TEXT_BASE for linking the SPL binary */
-#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
-
-/* Stack size for SPL */
-#define CONFIG_SPL_STACK_SIZE (4 * 1024)
-
-/* MALLOC size for SPL */
-#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
-
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-
-#define CHUNKSZ_CRC32 (1 * 1024)
-
-#define CONFIG_CRC32_VERIFY
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+#include <configs/socfpga_common.h>
-/* Support for common/libcommon.o in SPL binary */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-/* Support for lib/libgeneric.o in SPL binary */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define ALTERA_BOARD_NAME "Altera SOCFPGA Cyclone5 Board"
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
new file mode 100644
index 0000000..27e0261
--- /dev/null
+++ b/include/configs/socfpga_socrates.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2014 Pavel Machek <pavel at denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#include <configs/socfpga_common.h>
+
+#define ALTERA_BOARD_NAME "EBV SoCrates - Cyclone V SoC FPGA Board"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/socfpga_virtual.h b/include/configs/socfpga_virtual.h
new file mode 100644
index 0000000..cf871e2
--- /dev/null
+++ b/include/configs/socfpga_virtual.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2014 Pavel Machek <pavel at denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#include <configs/socfpga_common.h>
+
+#define ALTERA_BOARD_NAME "SOCFPGA Virtual Board"
+
+#endif /* __CONFIG_H */
diff --git a/lib/time.c b/lib/time.c
index 73c3b6a..7ac00e9 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -15,7 +15,7 @@
#endif
#ifndef CONFIG_WD_PERIOD
-# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default*/
+# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -55,7 +55,9 @@ static unsigned long long notrace tick_to_time(uint64_t tick)
{
unsigned int div = get_tbclk();
- tick *= CONFIG_SYS_HZ;
+ do_div(tick, 1000);
+ do_div(tick, 20);
+ // tick /= CONFIG_SYS_HZ;
do_div(tick, div);
return tick;
}
diff --git a/mkit b/mkit
new file mode 100755
index 0000000..903b059
--- /dev/null
+++ b/mkit
@@ -0,0 +1,9 @@
+#!/bin/bash
+eval ` eldk-switch.sh -r 5.2 armv7a`
+#make mrproper socfpga_cyclone5_config
+#make mrproper socfpga_socrates_config
+make u-boot.img && \
+cp u-boot.bin /tftpboot/wagabuibui
+# u-boot SPL does not compile for wagabuibui
+# make spl/u-boot-spl.bin && \
+# scp u-boot.bin pavel at pollux.denx.de:~/mainline-altera/boot
diff --git a/net/bootp.c b/net/bootp.c
index 189a003..745a03b 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -623,8 +623,7 @@ BootpRequest(void)
rand_ms = rand() >> 19;
printf("Random delay: %ld ms...\n", rand_ms);
- for (i = 0; i < rand_ms; i++)
- udelay(1000); /*Wait 1ms*/
+ mdelay(rand_ms);
#endif /* CONFIG_BOOTP_RANDOM_DELAY */
diff --git a/net/eth.c b/net/eth.c
index 99386e3..d5e6554 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -181,8 +181,12 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
if (dev->write_hwaddr &&
!eth_mac_skip(eth_number)) {
- if (!is_valid_ether_addr(dev->enetaddr))
- return -1;
+ if (!is_valid_ether_addr(dev->enetaddr)) {
+ printf("\nError: %s ethernet address not valid: %pM\n",
+ dev->name, dev->enetaddr);
+ /* return -1; */
+ memcpy(dev->enetaddr, "\12\23\34\46\56\60", 6);
+ }
ret = dev->write_hwaddr(dev);
}
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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