[U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes

[Siarhei Siamashka]

Hello,

First of all, it may be worth reminding that no accurate documentation
for this particular DRAM controller exists in public access.

However it is suspected that Allwinner uses one of the revisions of
Synopsys DesignWare DDR2/3-Lite Memory Controller IP (MCTL) combined
with DDR2/3-Lite PHY IP in A10/A13/A20. Also this DRAM controller
apparently has siblings in Rockchip RK29XX, RK30XX and TI KeyStone2
hardware, which have some documentation and some bits of kernel and
bootloader sources available in the Internet. Not to mention the
original Allwinner boot0 bootloader sources and the suspend support
code from the linux-sunxi kernel. This provides enough hints for
finding out how the DRAM controller actually works by checking
various bits of information via the trial and error method.

In other words, a few people from the linux-sunxi community (me included)
are essentially doing reverse engineering of the DRAM controller and using
the linux-sunxi wiki to document all the findings:
   http://linux-sunxi.org/DRAM_Controller

If Allwinner Technology, Synopsys DesignWare or anyone else can share
real documentation or at least provide some hints or review the code,
that would be really appreciated.

Nevertheless, here is a patch set, which tries to improve the current
u-boot sunxi dram code in the following way:
 * remove the convoluted dead code paths, which have no real use
 * fix obvious bugs and timing violations
 * add real ZQ calibration and ODT support for better reliability
   and higher clock speed potential
 * remove duplication and share code between sun4i/sun5i/sun7i
 * add more configuration knobs (such as MBUS clock frequency)
 * optional support for automatic detection of the bus width and
   chip density

This patch set only modifies the dram.c and dram.h source files and
applies cleanly to u-boot v2014.07 (but is intended for v2014.10).
The patch set is organized in such a way, that we first fix bugs in
the current sun7i implementation, and only after that add the missing
sun4i/sun5i support bits. As such, it clashes with the dram parts
of the sun4i/sun5i support patches, earlier submitted by Hans de Goede.

Most of this work has been done during the last 3 months (and apart
from the u-boot patches, it also includes improving the DRAM controler
documentation in the wiki and developing extra tools, which assist
in finding optimal DRAM configuration for each device). Many thanks
to Jens Kuske, who helped really a lot in brainstorming and testing.

To sum it up, the main purpose of these patches is to provide:
1) The potential ability to have a universal generic failsafe DRAM
   initialization for all Allwinner A10/A13/A20 devices using the
   same u-boot binary (or at least the same SPL)
2) The configuration knobs, which allow to reach extreme clock speeds
   and maximize performance for the selected boards with the help of
   extra tuning.

These patches are also available at:
   https://github.com/ssvb/u-boot-sunxi-dram/commits/sunxi-dram-fixes

As a demonstration, there is also a highly experimental test branch with
the DRAM performance tuning for the Cubietruck board (initially targeting
600 MHz DRAM clock speed, up from the current 432 MHz), which is
compatible with the sunxi-3.4 kernel:
   https://github.com/ssvb/u-boot-sunxi-dram/commits/highspeedtruck-sunxi-3.4
Or alternatively, a similar branch for the mainline 3.16 kernel:
   https://github.com/ssvb/u-boot-sunxi-dram/commits/highspeedtruck-mainline-3.16

The 600 MHz clock speed is clearly an overkill and may not work on every
device, so we will have to settle with something more modest in the end.
But, for example, the DRAM in my Cubietruck can be clocked up to 648 MHz.
The preliminary DRAM parameters tuning instructions are available at:
   http://linux-sunxi.org/A10_DRAM_Controller_Calibration


Siarhei Siamashka (14):
  sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
  sunxi: dram: Remove broken super-standby remnants
  sunxi: dram: Respect the DDR3 reset timing requirements
  sunxi: dram: Code cleanup and comments for the CKE delay handling
  sunxi: dram: Code cleanup for the impedance calibration
  sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
  sunxi: dram: Use divisor P=1 for PLL5
  sunxi: dram: Improve DQS gate data training error handling
  sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
  sunxi: dram: Configurable DQS gating window mode and delay
  sunxi: dram: Support sun4i (Allwinner A10) and sun5i (Allwinner A13)
  sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
  sunxi: dram: Derive write recovery delay from DRAM clock speed
  sunxi: dram: Autodetect DDR3 bus width and density

 arch/arm/cpu/armv7/sunxi/dram.c        | 606 ++++++++++++++++++++-------------
 arch/arm/include/asm/arch-sunxi/dram.h |  11 +-
 2 files changed, 374 insertions(+), 243 deletions(-)

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1.8.3.2