[U-Boot] [PATCH 06/14] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)

[Ian Campbell]

On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
> The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed.
> Allwinner A13 uses only 16-bit data bus width to connect the external DRAM,
> which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so
> it does not make much sense to clock a wider internal bus at a very high speed.
> The Allwinner A13 manual specifies 300 MHz MBUS clock speed limit and 533 MHz
> DRAM clock speed limit. Newer sun7i hardware (Allwinner A20) has a full width
> 32-bit external memory interface again, but still keeps the MBUS clock speed
> configurable. Clocking MBUS too low inhibits memory performance and one has
> to find the optimal MBUS/DRAM clock speed ratio, which may depend on many
> factors.
> 
> This patch introduces a new 'mbus_clock' parameter for the 'dram_para' struct
> and uses it as a desired MBUS clock speed target. If 'mbus_clock' is not set,
> 300 MHz is used by default to match the older hardcoded settings.

Nothing in this series seems to set it for any board -- is that
expected?

> +	if (pll6x_div <= 16 && pll6x_clk / pll6x_div > pll5p_clk / pll5p_div) {

Some brackets or perhaps some temporaries ({pll5p,pll6x}_rate ?) might
help clarity/readability here.

When pll6 is viable you prefer the faster clock, even if it might happen
to be further from the requested clock, is that right? Or does all the
arithmetic end up with that never being the case?

Ian.