[U-Boot] [PATCH V4] ARM: mx6: Add support for Kosagi Novena

[Nikolay Dimitrov]

Hi Marek, Sean,

Do you have any comments on the PHY signal driving conflict and reset 
timing issue (see below)?

On 09/24/2014 05:46 AM, Nikolay Dimitrov wrote:
> There's one more issue here - when you get the PHY out of reset, you'll
> have to both de-assert the RESET line while keeping the strapping
> signals stable so the PHY can read them, but at the same time the PHY RX
> pins are becoming outputs and driving the same lines, which is not good.
...
>
> Here's my proposal how to fix both (line driving conflict and reset
> timing) issues:
>
> #define ENET_PHY_CFG_PC \
>      (PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE)
>
> static iomux_v3_cfg_t enet_pads1[] = {
>      MX6_PAD_ENET_MDIO__ENET_MDIO    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>
>      MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL| MUX_PAD_CTRL(ENET_PAD_CTRL),
>      MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
>
>      /* pin 35, PHY_AD2 */
>      MX6_PAD_RGMII_RXC__GPIO6_IO30    | MUX_PAD_CTRL(ENET_PHY_CFG_PC),
>      /* pin 32, MODE0 */
>      MX6_PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(ENET_PHY_CFG_PC),
>      /* pin 31, MODE1 */
>      MX6_PAD_RGMII_RD1__GPIO6_IO27    | MUX_PAD_CTRL(ENET_PHY_CFG_PC),
>      /* pin 28, MODE2 */
>      MX6_PAD_RGMII_RD2__GPIO6_IO28    | MUX_PAD_CTRL(ENET_PHY_CFG_PC),
>      /* pin 27, MODE3 */
>      MX6_PAD_RGMII_RD3__GPIO6_IO29    | MUX_PAD_CTRL(ENET_PHY_CFG_PC),
>      /* pin 33, CLK125_EN */
>      MX6_PAD_RGMII_RX_CTL__GPIO6_IO24| MUX_PAD_CTRL(ENET_PHY_CFG_PC),
>
>      /* PHY nRST */
>      MX6_PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL),
> };
>
> static void novena_spl_setup_iomux_enet(void)
> {
>      imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
>
>      /* Assert Ethernet PHY nRST */
>      gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
>
>      /* Using imx6 internal pull-ups to drive PHY config pins during PHY
> reset */
>      gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
>      gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
>      gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
>      gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
>      gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
>      gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
>
>      /* Interpreting fig.8 from the PHY datasheet */
>      mdelay(10);
>
>      /* De-assert Ethernet PHY nRST */
>      gpio_set_value(IMX_GPIO_NR(3, 23), 1);
>
>      /* After PHY is configured, we can finally connect our FEC */
>      imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
>
>      /* PHY datasheet recommends on p.53 to wait at least 100us before
> using MII, so we enforce this delay here */
>      udelay(100);
> }

Kind regards,
Nikolay