[U-Boot] [PATCH 4/4] x86: queensbay: Implement PIRQ routing
Bin Meng
bmeng.cn at gmail.com
Fri Apr 24 05:36:47 CEST 2015
Hi Simon,
On Fri, Apr 24, 2015 at 11:02 AM, Simon Glass <sjg at chromium.org> wrote:
> Hi Bin,
>
> On 21 April 2015 at 19:56, Bin Meng <bmeng.cn at gmail.com> wrote:
>> Implement Intel Queensbay platform-specific PIRQ routing support.
>> The chipset PIRQ routing setup is called in the arch_mist_init().
>
> arch_misc_init()?
Will fix.
> Also how can this be used on other boards? Should part of this code be
> moved to a generic place?
Generally Intel interrupt router should be compatible, but the offsets
of these interrupt routing registers might be different from platform
to platform. The platform-specific part is the internal PCI devices'
interrupt pin to PIRQ map.
>>
>> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>>
>> ---
>>
>> arch/x86/cpu/queensbay/Makefile | 2 +-
>> arch/x86/cpu/queensbay/irq.c | 236 +++++++++++++++++++++++++++
>> arch/x86/cpu/queensbay/tnc.c | 10 +-
>> arch/x86/include/asm/arch-queensbay/device.h | 94 +++++++++++
>> arch/x86/include/asm/arch-queensbay/irq.h | 55 +++++++
>> arch/x86/include/asm/arch-queensbay/tnc.h | 26 ++-
>> arch/x86/include/asm/u-boot-x86.h | 2 +
>> configs/crownbay_defconfig | 1 +
>> include/configs/crownbay.h | 1 +
>> 9 files changed, 423 insertions(+), 4 deletions(-)
>> create mode 100644 arch/x86/cpu/queensbay/irq.c
>> create mode 100644 arch/x86/include/asm/arch-queensbay/device.h
>> create mode 100644 arch/x86/include/asm/arch-queensbay/irq.h
>>
>> diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
>> index d8761fd..4599a48 100644
>> --- a/arch/x86/cpu/queensbay/Makefile
>> +++ b/arch/x86/cpu/queensbay/Makefile
>> @@ -5,5 +5,5 @@
>> #
>>
>> obj-y += fsp_configs.o
>> -obj-y += tnc.o topcliff.o
>> +obj-y += irq.o tnc.o topcliff.o
>> obj-$(CONFIG_PCI) += tnc_pci.o
>> diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
>> new file mode 100644
>> index 0000000..cf433d3
>> --- /dev/null
>> +++ b/arch/x86/cpu/queensbay/irq.c
>> @@ -0,0 +1,236 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn at gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <errno.h>
>> +#include <malloc.h>
>> +#include <asm/io.h>
>> +#include <asm/pci.h>
>> +#include <asm/post.h>
>> +#include <asm/processor.h>
>> +#include <asm/pirq_routing.h>
>> +#include <asm/arch/device.h>
>> +#include <asm/arch/tnc.h>
>> +#include <asm/arch/irq.h>
>> +
>> +static struct irq_routing_table *pirq_routing_table;
>> +
>> +bool pirq_check_irq_routed(int link, u8 irq)
>> +{
>> + u8 pirq;
>> +
>> + pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
>> + pirq &= 0xf;
>> +
>> + /* IRQ# 0/1/2/8/13 are reserved */
>> + if (pirq < 3 || pirq == 8 || pirq == 13)
>> + return false;
>> +
>> + return pirq == irq ? true : false;
>> +}
>> +
>> +int pirq_translate_link(int link)
>> +{
>> + return LINK_V2N(link);
>> +}
>> +
>> +void pirq_assign_irq(int link, u8 irq)
>> +{
>> + /* IRQ# 0/1/2/8/13 are reserved */
>> + if (irq < 3 || irq == 8 || irq == 13)
>> + return;
>> +
>> + x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
>> +}
>> +
>> +static inline void fill_irq_info(struct irq_info **slot, int *entries, u8 bus,
>> + u8 device, u8 func, u8 pin, u8 pirq)
>> +{
>
> Please declare a local variable
>
> struct irq_info *slot = *slotp;
>
> and rename the param to slotp, to avoid the first four (*slot).
Will fix.
>> + (*slot)->bus = bus;
>> + (*slot)->devfn = (device << 3) | func;
>> + (*slot)->irq[pin - 1].link = LINK_N2V(pirq);
>> + (*slot)->irq[pin - 1].bitmap = PIRQ_BITMAP;
>> + (*entries)++;
>> + (*slot)++;
>> +}
>> +
>> +/* PCIe port downstream INTx swizzle */
>> +static inline u8 pin_swizzle(u8 pin, int port)
>> +{
>> + return (pin + port) % 4;
>> +}
>> +
>> +__weak int board_fill_irq_info(struct irq_info *slot)
>> +{
>> + return 0;
>> +}
>> +
>> +static int create_pirq_routing_table(void)
>> +{
>> + struct irq_routing_table *rt;
>> + struct irq_info *slot;
>> + int irq_entries = 0;
>> + pci_dev_t tcf_bdf;
>> + u8 tcf_bus, bus;
>> + int i;
>> +
>> + rt = malloc(sizeof(struct irq_routing_table));
>> + if (!rt)
>> + return -ENOMEM;
>> + memset((char *)rt, 0, sizeof(struct irq_routing_table));
>> +
>> + /* Populate the PIRQ table fields */
>> + rt->signature = PIRQ_SIGNATURE;
>> + rt->version = PIRQ_VERSION;
>> + rt->rtr_bus = 0;
>> + rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC;
>> + rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
>> + rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
>> +
>> + slot = rt->slots;
>> +
>> + /*
>> + * Now fill in the irq_info entries in the PIRQ table
>> + *
>> + * We start from internal TunnelCreek PCI devices first, then
>> + * followed by all the 4 PCIe ports downstream devices, including
>> + * the Queensbay platform Topcliff chipset devices.
>> + */
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV,
>> + TNC_IGD_FUNC, INTA, PIRQE);
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV,
>> + TNC_SDVO_FUNC, INTA, PIRQF);
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV,
>> + TNC_HDA_FUNC, INTA, PIRQG);
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV,
>> + TNC_PCIE0_FUNC, INTA, PIRQE);
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV,
>> + TNC_PCIE1_FUNC, INTA, PIRQF);
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV,
>> + TNC_PCIE2_FUNC, INTA, PIRQG);
>> + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV,
>> + TNC_PCIE3_FUNC, INTA, PIRQH);
>> +
>> + /* Check which PCIe port the Topcliff chipset is connected to */
>> + tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0);
>> + tcf_bus = PCI_BUS(tcf_bdf);
>> + for (i = 0; i < 4; i++) {
>> + bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0),
>> + PCI_SECONDARY_BUS);
>> + if (bus == tcf_bus)
>> + break;
>> + }
>> +
>> + /* Fill in the Topcliff chipset devices' irq info */
>> + if (i < 4) {
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV,
>> + TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i));
>> +
>> + tcf_bus++;
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
>> + TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
>> + TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
>> + TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
>> + TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
>> + TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
>> + TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
>> + TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
>> + TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
>> + TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6,
>> + TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
>> + TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
>> + TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
>> + TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
>> + TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
>> + TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
>> + TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
>> + TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
>> + TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
>> + TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
>> + TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
>> + TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
>> + TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
>> + TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
>> + TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i));
>> + }
>> +
>> + /* Call board-specific routine to fill in add-in card's irq info */
>> + irq_entries += board_fill_irq_info(slot);
>
> But isn't this already board-specific code?
This codes are put in the platform directory (arch/cpu/queensbay). We
should implement board_fill_irq_info() in board directory
(board/intel/crownbay) for any add-in cards.
>> +
>> + rt->size = irq_entries * sizeof(struct irq_info) + 32;
>> +
>> + pirq_routing_table = rt;
>> +
>> + return 0;
>> +}
>> +
>> +void pirq_init(void)
>> +{
>> + u32 rcba;
>> +
>> + rcba = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
>> + rcba &= ~MEM_BAR_EN;
>> +
>> + /* Make sure all internal PCI devices are using INTA */
>> + writel(INTA, rcba + D02IP);
>> + writel(INTA, rcba + D03IP);
>> + writel(INTA, rcba + D27IP);
>> + writel(INTA, rcba + D31IP);
>> + writel(INTA, rcba + D23IP);
>> + writel(INTA, rcba + D24IP);
>> + writel(INTA, rcba + D25IP);
>> + writel(INTA, rcba + D26IP);
>> +
>> + /*
>> + * Route TunnelCreek PCI device interrupt pin to PIRQ
>> + *
>> + * Since PCIe downstream ports received INTx are routed to PIRQ
>> + * A/B/C/D directly and not configurable, we route internal PCI
>> + * device's INTx to PIRQ E/F/G/H.
>> + */
>> + writew(PIRQE, rcba + D02IR);
>> + writew(PIRQF, rcba + D03IR);
>> + writew(PIRQG, rcba + D27IR);
>> + writew(PIRQH, rcba + D31IR);
>> + writew(PIRQE, rcba + D23IR);
>> + writew(PIRQF, rcba + D24IR);
>> + writew(PIRQG, rcba + D25IR);
>> + writew(PIRQH, rcba + D26IR);
>> +
>> + if (!create_pirq_routing_table()) {
>
> Can you add a comment here as to why you do this next bit if
> create_pirq_routing_table() fails?
I am not sure if you misread the codes? If create_pirq_routing_table()
fails, it returns non-zero value and the following pirq_route_irqs()
will not be called.
>> + /* Route PIRQ */
>> + pirq_route_irqs(pirq_routing_table->slots,
>> + get_irq_slot_count(pirq_routing_table));
>> + }
>> +}
>> +
>> +u32 write_pirq_routing_table(u32 addr)
>> +{
>> + return copy_pirq_routing_table(addr, pirq_routing_table);
>> +}
>> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
>> index f756a0d..b46a7e9 100644
>> --- a/arch/x86/cpu/queensbay/tnc.c
>> +++ b/arch/x86/cpu/queensbay/tnc.c
>> @@ -8,7 +8,8 @@
>> #include <asm/io.h>
>> #include <asm/pci.h>
>> #include <asm/post.h>
>> -#include <asm/arch/tnc.h>
>> +#include <asm/arch/device.h>
>> +#include <asm/arch/irq.h>
>> #include <asm/fsp/fsp_support.h>
>> #include <asm/processor.h>
>>
>> @@ -43,3 +44,10 @@ int arch_cpu_init(void)
>>
>> return 0;
>> }
>> +
>> +int arch_misc_init(void)
>> +{
>> + pirq_init();
>> +
>> + return 0;
>> +}
>> diff --git a/arch/x86/include/asm/arch-queensbay/device.h b/arch/x86/include/asm/arch-queensbay/device.h
>> new file mode 100644
>> index 0000000..953b48f
>> --- /dev/null
>> +++ b/arch/x86/include/asm/arch-queensbay/device.h
>> @@ -0,0 +1,94 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn at gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef _QUEENSBAY_DEVICE_H_
>> +#define _QUEENSBAY_DEVICE_H_
>> +
>> +#include <pci.h>
>> +
>> +/* TunnelCreek PCI Devices */
>> +#define TNC_HOST_BRIDGE_DEV 0
>> +#define TNC_HOST_BRIDGE_FUNC 0
>> +#define TNC_IGD_DEV 2
>> +#define TNC_IGD_FUNC 0
>> +#define TNC_SDVO_DEV 3
>> +#define TNC_SDVO_FUNC 0
>> +#define TNC_PCIE0_DEV 23
>> +#define TNC_PCIE0_FUNC 0
>> +#define TNC_PCIE1_DEV 24
>> +#define TNC_PCIE1_FUNC 0
>> +#define TNC_PCIE2_DEV 25
>> +#define TNC_PCIE2_FUNC 0
>> +#define TNC_PCIE3_DEV 26
>> +#define TNC_PCIE3_FUNC 0
>> +#define TNC_HDA_DEV 27
>> +#define TNC_HDA_FUNC 0
>> +#define TNC_LPC_DEV 31
>> +#define TNC_LPC_FUNC 0
>> +
>> +#define TNC_HOST_BRIDGE \
>> + PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
>> +#define TNC_IGD \
>> + PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
>> +#define TNC_SDVO \
>> + PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
>> +#define TNC_PCIE0 \
>> + PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
>> +#define TNC_PCIE1 \
>> + PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
>> +#define TNC_PCIE2 \
>> + PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
>> +#define TNC_PCIE3 \
>> + PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
>> +#define TNC_HDA \
>> + PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
>> +#define TNC_LPC \
>> + PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
>> +
>> +/* Topcliff IOH PCI Devices */
>> +#define TCF_PCIE_PORT_DEV 0
>> +#define TCF_PCIE_PORT_FUNC 0
>> +
>> +#define TCF_DEV_0 0
>> +#define TCF_PKT_HUB_FUNC 0
>> +#define TCF_GBE_FUNC 1
>> +#define TCF_GPIO_FUNC 2
>> +
>> +#define TCF_DEV_2 2
>> +#define TCF_USB1_OHCI0_FUNC 0
>> +#define TCF_USB1_OHCI1_FUNC 1
>> +#define TCF_USB1_OHCI2_FUNC 2
>> +#define TCF_USB1_EHCI_FUNC 3
>> +#define TCF_USB_DEVICE_FUNC 4
>> +
>> +#define TCF_DEV_4 4
>> +#define TCF_SDIO0_FUNC 0
>> +#define TCF_SDIO1_FUNC 1
>> +
>> +#define TCF_DEV_6 6
>> +#define TCF_SATA_FUNC 0
>> +
>> +#define TCF_DEV_8 8
>> +#define TCF_USB2_OHCI0_FUNC 0
>> +#define TCF_USB2_OHCI1_FUNC 1
>> +#define TCF_USB2_OHCI2_FUNC 2
>> +#define TCF_USB2_EHCI_FUNC 3
>> +
>> +#define TCF_DEV_10 10
>> +#define TCF_DMA1_FUNC 0
>> +#define TCF_UART0_FUNC 1
>> +#define TCF_UART1_FUNC 2
>> +#define TCF_UART2_FUNC 3
>> +#define TCF_UART3_FUNC 4
>> +
>> +#define TCF_DEV_12 12
>> +#define TCF_DMA2_FUNC 0
>> +#define TCF_SPI_FUNC 1
>> +#define TCF_I2C_FUNC 2
>> +#define TCF_CAN_FUNC 3
>> +#define TCF_1588_FUNC 4
>> +
>> +#endif /* _QUEENSBAY_DEVICE_H_ */
>> diff --git a/arch/x86/include/asm/arch-queensbay/irq.h b/arch/x86/include/asm/arch-queensbay/irq.h
>> new file mode 100644
>> index 0000000..e7f8616
>> --- /dev/null
>> +++ b/arch/x86/include/asm/arch-queensbay/irq.h
>> @@ -0,0 +1,55 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn at gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef _ARCH_IRQ_H_
>> +#define _ARCH_IRQ_H_
>> +
>> +enum pci_int_pin {
>> + INTX,
>> + INTA,
>> + INTB,
>> + INTC,
>> + INTD
>> +};
>> +
>> +enum pirq_pin {
>> + PIRQA,
>> + PIRQB,
>> + PIRQC,
>> + PIRQD,
>> + PIRQE,
>> + PIRQF,
>> + PIRQG,
>> + PIRQH
>> +};
>> +
>> +/* PIRQ link number and value conversion */
>> +#define LINK_V2N(link) (link - 0x60)
>> +#define LINK_N2V(link) (link + 0x60)
>> +
>> +#define PIRQ_BITMAP 0xdee0
>> +
>> +struct irq_info;
>> +
>> +/**
>> + * board_fill_irq_info() - Board-specific irq_info fill routine
>> + *
>> + * This fills the irq_info table for any board-specific add-in cards.
>> + *
>> + * @slot: pointer to the struct irq_info that is to be filled in
>> + * @return: number of entries were written to the struct irq_info
>> + */
>> +int board_fill_irq_info(struct irq_info *slot);
>> +
>> +/**
>> + * pirq_init() - Initialize platform PIRQ routing
>> + *
>> + * This initializes the PIRQ routing on the platform and configures all PCI
>> + * devices' interrupt line register to a working IRQ number on the 8259 PIC.
>> + */
>> +void pirq_init(void);
>> +
>> +#endif /* _ARCH_IRQ_H_ */
>> diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
>> index 10ea51d..2535fe8 100644
>> --- a/arch/x86/include/asm/arch-queensbay/tnc.h
>> +++ b/arch/x86/include/asm/arch-queensbay/tnc.h
>> @@ -7,8 +7,30 @@
>> #ifndef _X86_ARCH_TNC_H_
>> #define _X86_ARCH_TNC_H_
>>
>> -#include <pci.h>
>> +/* Memory BAR Enable */
>> +#define MEM_BAR_EN 0x00000001
>>
>> -#define TNC_LPC PCI_BDF(0, 31, 0)
>> +/* LPC PCI Configuration Registers */
>> +#define LPC_RCBA 0xf0
>> +
>> +/* Interupt Pin Configuration (in RCBA) */
>> +#define D02IP 0x3118
>> +#define D03IP 0x3130
>> +#define D23IP 0x312c
>> +#define D24IP 0x3128
>> +#define D25IP 0x3124
>> +#define D26IP 0x3120
>> +#define D27IP 0x3110
>> +#define D31IP 0x3100
>> +
>> +/* Interupt Route Configuration (in RCBA) */
>> +#define D02IR 0x3160
>> +#define D03IR 0x3162
>> +#define D23IR 0x3150
>> +#define D24IR 0x314e
>> +#define D25IR 0x314c
>> +#define D26IR 0x314a
>> +#define D27IR 0x3148
>> +#define D31IR 0x3140
>
> Can we use a C structure for the RCBA, or part of it?
Yes, we can.
>>
>> #endif /* _X86_ARCH_TNC_H_ */
>> diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
>> index c743efd..122e054 100644
>> --- a/arch/x86/include/asm/u-boot-x86.h
>> +++ b/arch/x86/include/asm/u-boot-x86.h
>> @@ -53,6 +53,8 @@ int video_bios_init(void);
>> void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
>> void board_init_f_r(void) __attribute__ ((noreturn));
>>
>> +int arch_misc_init(void);
>> +
>> /* Read the time stamp counter */
>> static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
>> {
>> diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
>> index ce90553..47763f9 100644
>> --- a/configs/crownbay_defconfig
>> +++ b/configs/crownbay_defconfig
>> @@ -4,3 +4,4 @@ CONFIG_TARGET_CROWNBAY=y
>> CONFIG_OF_CONTROL=y
>> CONFIG_OF_SEPARATE=y
>> CONFIG_DEFAULT_DEVICE_TREE="crownbay"
>> +CONFIG_GENERATE_PIRQ_TABLE=y
>> diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
>> index 42042d1..4fef433 100644
>> --- a/include/configs/crownbay.h
>> +++ b/include/configs/crownbay.h
>> @@ -15,6 +15,7 @@
>>
>> #define CONFIG_SYS_MONITOR_LEN (1 << 20)
>> #define CONFIG_BOARD_EARLY_INIT_F
>> +#define CONFIG_ARCH_MISC_INIT
>>
>> #define CONFIG_NR_DRAM_BANKS 1
>>
>> --
Regards,
Bin
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